PSMN1R5-25YL Datasheet, PDF (1/13 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

PSMN1R5-25YL
N-channel TrenchMOS logic level FET
Rev. 01 — 16 June 2009
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
industrial and communications applications.
1.2 Features and benefits
„ High efficiency due to low switching
and conduction losses
„ Suitable for logic level gate drive
sources
1.3 Applications
„ Class-D amplifiers
„ DC-to-DC converters
„ Motor control
„ Server power supplies
1.4 Quick reference data
Table 1. Quick reference
Symbol Parameter
Conditions
Min Typ Max Unit
V_DS
drain-source voltage T_j ≥ 25 °C; T_j ≤ 150 °C
-
-
25 V
I_D
drain current
T_mb = 25 °C; V_GS = 10 V; [1] -
-
100 A
see Figure 1;
P_tot
total power
dissipation
T_mb = 25 °C; see Figure 2
-
-
109 W
Dynamic characteristics
Q_GD
gate-drain charge V_GS = 4.5 V; I_D = 10 A;
V_DS = 12 V; see Figure 14;
see Figure 15
-
9.2 -
nC
Q_G(tot) total gate charge
V_GS = 4.5 V; I_D = 10 A;
V_DS = 12 V; see Figure 14;
see Figure 15
-
36 -
nC
Static characteristics
R_DSon
drain-source
V_GS = 10 V; I_D = 15 A;
on-state resistance T_j = 25 °C
-
1.13 1.5 mΩ
[1] Continuous current is limited by package.