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| PSMN075-100MSE Datasheet, PDF (6/13 Pages) NXP Semiconductors – N-channel 100 V 71 m standard level MOSFET in LFPAK33 designed specifically for PoE applications | |||
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NXP Semiconductors
PSMN075-100MSE
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33 designed
specifically for PoE applications
Symbol
Parameter
Conditions
Dynamic characteristics
QG(tot)
total gate charge
ID = 5 A; VDS = 50 V; VGS = 10 V;
Tj = 25 °C; Fig. 14; Fig. 15
ID = 0 A; VDS = 0 V; VGS = 10 V;
Tj = 25 °C
QGS
QGS(th)
gate-source charge
pre-threshold gate-
source charge
ID = 5 A; VDS = 50 V; VGS = 10 V;
Tj = 25 °C; Fig. 14; Fig. 15
QGS(th-pl)
post-threshold gate-
source charge
QGD
gate-drain charge
ID = 5 A; VDS = 50 V; VGS = 10 V;
Tj 25 °C; Fig. 14; Fig. 15
VGS(pl)
gate-source plateau
voltage
ID = 5 A; VDS = 50 V; Tj = 25 °C;
Fig. 14; Fig. 15
Ciss
input capacitance
VDS = 50 V; VGS = 0 V; f = 1 MHz;
Coss
output capacitance
Tj = 25 °C; Fig. 16
Crss
reverse transfer
capacitance
td(on)
tr
turn-on delay time
rise time
VDS = 50 V; RL = 10 Ω; VGS = 10 V;
RG(ext) = 5 Ω; Tj = 25 °C
td(off)
turn-off delay time
tf
fall time
Source-drain diode
VSD
source-drain voltage IS = 15 A; VGS = 0 V; Tj = 25 °C; Fig. 17
trr
reverse recovery time IS = 5 A; dIS/dt = -100 A/µs; VGS = 0 V;
Qr
recovered charge
VDS = 50 V; Tj = 25 °C
Min Typ Max Unit
-
16.4 -
nC
-
12.9 -
nC
-
3.1 -
nC
-
2.1 -
nC
-
1
-
nC
-
5.3 -
nC
-
4.3 -
V
-
773 -
pF
-
66
-
pF
-
48
-
pF
-
5.5 -
ns
-
5.8 -
ns
-
12.4 -
ns
-
6.2 -
ns
-
0.89 1.2 V
-
35.8 -
ns
-
50.7 -
nC
PSMN075-100MSE
Product data sheet
All information provided in this document is subject to legal disclaimers.
26 March 2013
© NXP B.V. 2013. All rights reserved
6 / 13
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