74HC595BQ115 Datasheet, PDF(6/24 Page) NXP Semiconductors – 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

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74HC595BQ115 Datasheet, PDF (6/24 Pages) NXP Semiconductors – 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

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NXP Semiconductors

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches;

3-state

SHCP

STCP

Z-state

Q7S

Fig 8. Timing diagram

Z-state

mna556

8. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min Max Unit

VCC

supply voltage

IIK

input clamping current

IOK

output clamping current

output current

VI < ï0.5 V or VI > VCC + 0.5 V

VO < ï0.5 V or VO > VCC + 0.5 V

VO = ï0.5 V to (VCC + 0.5 V)

pin Q7S

ï0.5 +7

ï±20 mA

ï±25 mA

pins Qn

ï±35 mA

ICC

IGND

Tstg

Ptot

supply current

ground current

storage temperature

total power dissipation

DIP16 package

ï70 -

ï65 +150 ï°C

[1] -

750 mW

SO16 package

[2] -

500 mW

SSOP16 package

[3] -

500 mW

TSSOP16 package

[3] -

500 mW

DHVQFN16 package

[4] -

500 mW

[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 ï°C.

[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 ï°C.

[3] For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 ï°C.

[4] For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 ï°C.

74HC_HCT595

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 6 â 12 December 2011

6 of 24

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