P89V660 Datasheet, PDF (58/89 Pages) NXP Semiconductors – 8-bit 80C51 5 V low power 16 kB/32 kB/64 kB flash microcontroller with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI

NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I²C-bus, SPI
The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a
capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit
enables the positive edge. If both bits are set both edges will be enabled and a capture will
occur for either transition.
The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function.
There are two additional registers associated with each of the PCA modules. They are
CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a
capture occurs or a compare should occur. When a module is used in the PWM mode
these registers are used to control the duty cycle of the output.
PCA TIMER/COUNTER
CF CR
CCON
-
CCF4 CCF3 CCF2 CCF1 CCF0 _(C0h)
MODULE0
MODULE1
MODULE2
MODULE3
MODULE4
IEN0.6
EC
IEN0.7
EA
to
interrupt
priority
decoder
CMOD.0 ECF
Fig 27. PCA interrupt system
CCAPMn.0
ECCFn
002aab914
Table 45. CMOD - PCA counter mode register (address C1H) bit allocation
Not bit addressable; Reset value: 00H
Bit
7
6
5
4
3
2
1
Symbol CIDL WDTE
-
-
-
CPS1 CPS0
0
ECF
P89V660_662_664_1
Product data sheet
Rev. 01 — 2 May 2007
© NXP B.V. 2007. All rights reserved.
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