P89V660 Datasheet, PDF (54/89 Pages) NXP Semiconductors – 8-bit 80C51 5 V low power 16 kB/32 kB/64 kB flash microcontroller with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI

NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I²C-bus, SPI
pin is the clock output and input for the master and slave modes, respectively. The SPI
clock generator will start following a write to the master devices SPI data register. The
written data is then shifted out of the MOSI pin on the master device into the MOSI pin of
the slave device. Following a complete transmission of one byte of data, the SPI clock
generator is stopped and the SPIF flag is set. An SPI interrupt request will be generated if
the SPI Interrupt Enable bit (SPIE) and the SPI interrupt enable bit, ES3, are both set.
An external master drives the Slave Select input pin, SS LOW to select the SPI module as
a slave. If SS has not been driven LOW, then the slave SPI unit is not active and the MOSI
pin can also be used as an input port pin.
CPHA and CPOL control the phase and polarity of the SPI clock. Figure 24 and Figure 25
show the four possible combinations of these two bits.
MSB master LSB
8-BIT SHIFT REGISTER
MISO MISO
MOSI MOSI
MSB slave LSB
8-BIT SHIFT REGISTER
SPI
CLOCK GENERATOR
Fig 23. SPI master-slave interconnection
SCK
SS
SCK
SS
V_DD V_SS
002aaa528
Table 40. SPCR - SPI control register (address D5H) bit allocation
Bit addressable; Reset source(s): any reset; Reset value: 0000 0000B
Bit
7
6
5
4
3
2
Symbol SPIE SPEN DORD MSTR CPOL CPHA
1
SPR1
0
SPR0
Table 41.
Bit
7
6
5
4
3
SPCR - SPI control register (address D5H) bit description
Symbol
Description
SPIE
If both SPIE and ES3 are set to one, SPI interrupts are enabled.
SPEN
SPI enable bit. When set enables SPI.
DORD
Data transmission order. 0 = MSB first; 1 = LSB first in data
transmission.
MSTR
Master/slave select. 1 = master mode, 0 = slave mode.
CPOL
Clock polarity. 1 = SCK is high when idle (active LOW), 0 = SCK is low
when idle (active HIGH).
P89V660_662_664_1
Product data sheet
Rev. 01 — 2 May 2007
© NXP B.V. 2007. All rights reserved.
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