P89V660 Datasheet, PDF (55/89 Pages) NXP Semiconductors – 8-bit 80C51 5 V low power 16 kB/32 kB/64 kB flash microcontroller with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI

NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I²C-bus, SPI
Table 41.
Bit
2
1
0
SPCR - SPI control register (address D5H) bit description …continued
Symbol
Description
CPHA
Clock Phase control bit. 1 = shift triggered on the trailing edge of the
clock; 0 = shift triggered on the leading edge of the clock.
SPR1
SPI Clock Rate Select bit 1. Along with SPR0 controls the SCK rate of
the device when a master. SPR1 and SPR0 have no effect on the
slave. See Table 42.
SPR0
SPI Clock Rate Select bit 0. Along with SPR1 controls the SCK rate of
the device when a master. SPR1 and SPR0 have no effect on the
slave. See Table 42.
Table 42.
SPR1
0
0
1
1
SPCR - SPI control register (address D5H) clock rate selection
SPR0
SCK = f_osc divided by
6-clock mode
12-clock mode
0
2
4
1
8
16
0
32
64
1
64
128
Table 43. SPSR - SPI status register (address AAH) bit allocation
Bit addressable; Reset source(s): any reset; Reset value: 0000 0000B
Bit
7
6
5
4
3
2
1
0
Symbol SPIF WCOL
-
-
-
-
-
-
Table 44.
Bit
7
6
5 to 0
SPSR - SPI status register (address AAH) bit description
Symbol
Description
SPIF
SPI interrupt flag. Upon completion of data transfer, this bit is set to ‘1’.
If SPIE = 1 and ES3 = 1, an interrupt is then generated. This bit is
cleared by software.
WCOL
Write Collision Flag. Set if the SPI data register is written to during
data transfer. This bit is cleared by software.
-
Reserved for future use. Should be set to ‘0’ by user programs.
SCK cycle #
(for reference)
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI
(from master)
MISO
(from slave)
SS (to slave)
1
2
3
4
5
6
7
8
MSB 6
5
4
3
2
1 LSB
MSB
6
5
4
3
2
1 LSB
Fig 24. SPI transfer format with CPHA = 0
002aaa529
P89V660_662_664_1
Product data sheet
Rev. 01 — 2 May 2007
© NXP B.V. 2007. All rights reserved.
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