P89V660 Datasheet, PDF (53/89 Pages) NXP Semiconductors – 8-bit 80C51 5 V low power 16 kB/32 kB/64 kB flash microcontroller with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI

NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I²C-bus, SPI
In a more complex system the following could be used to select slaves 1 and 2 while
excluding slave 0:
Example 1, slave 0:
SADDR = 1100 0000
-^S---^A--_G--^D--_i--_v-^E--_e-^N-_n-----₌₌-----₁₁---₁₁---₀₁---₀₁----₀-¹--_X-⁰---⁰-_X--¹-₀
(6)
Example 2, slave 1:
SADDR = 1110 0000
-^S---^A--_G--^D--_i--_v-^E--_e-^N-_n-----₌₌-----₁₁---₁₁---₁₁---₀₁----₀-¹--_X-⁰---¹-₀--⁰-_X
(7)
Example 2, slave 2:
SADDR = 1100 0000
-^S---^A--_G--^D--_i--_v-^E--_e-^N-_n-----₌₌-----₁₁---₁₁---₀₁---₀₁----₀-¹--₀-¹--_X-⁰---⁰-_X
(8)
In the above example the differentiation among the 3 slaves is in the lower 3 address bits.
Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1
requires that bit 1 = 0 and it can be uniquely addressed by 1110 0101. Slave 2 requires
that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude
Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2.
The Broadcast Address for each slave is created by taking the logical OR of SADDR and
SADEN. Zeros in this result are treated as don’t-cares. In most cases, interpreting the
don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR
and SADEN are loaded with 0s. This produces a given address of all ‘don’t cares’ as well
as a Broadcast address of all ‘don’t cares'. This effectively disables the Automatic
Addressing mode and allows the microcontroller to use standard UART drivers which do
not make use of this feature.
6.8 Serial Peripheral Interface (SPI)
6.8.1 SPI features
• Master or slave operation
• 10 MHz bit frequency (max)
• LSB first or MSB first data transfer
• Four programmable bit rates
• End of transmission (SPIF)
• Write collision flag protection (WCOL)
• Wake-up from Idle mode (slave mode only)
6.8.2 SPI description
The serial peripheral interface allows high-speed synchronous data transfer between the
P89V660/662/664 and peripheral devices or between several P89V660/662/664 devices.
Figure 23 shows the correspondence between master and slave SPI devices. The SCK
P89V660_662_664_1
Product data sheet
Rev. 01 — 2 May 2007
© NXP B.V. 2007. All rights reserved.
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