UJA1061_10 Datasheet, PDF (50/77 Pages) NXP Semiconductors – Fault-tolerant CAN/LIN fail-safe system basis chip

NXP Semiconductors
UJA1061
Fault-tolerant CAN/LIN fail-safe system basis chip
Table 26. Static characteristics^[1] …continued
T_vj = −40 °C to +150 °C; V_BAT42 = 5.5 V to 52 V;V_BAT14 = 5.5 V to 27 V; V_BAT42 ≥ V_BAT14 − 1 V; unless otherwise specified. All
voltages are defined with respect to ground. Positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
System inhibit output; pin SYSINH
V_{BAT42-SYSINH(drop)}
V_BAT42 to V_SYSINH
voltage drop
I_SYSINH = −0.2 mA
-
1.0
2.0
V
|I_L|
leakage current
V_SYSINH = 0 V
Inhibit / limp-home output; pin INH/LIMP
-
-
5
μA
V_{BAT14-INH(drop)}
V_BAT14 to V_INH voltage I_INH/LIMP = −10 μA;
drop
ILEN = ILC = 1
-
0.7
1.0
V
I_INH/LIMP = −200 μA;
ILEN = ILC = 1
-
1.2
2.0
V
I_o(INH/LIMP)
output current
capability
V_INH/LIMP = 0.4 V; ILEN = 1;
ILC = 0
0.8
-
4
mA
|I_L|
leakage current
V_INH/LIMP = 0 V to V_BAT14;
-
-
5
μA
ILEN = 0
Wake input; pin WAKE
V_th(WAKE)
WAKE voltage
threshold
2.0
3.3
5.2
V
I_WAKE(pu)
pull-up input current V_WAKE = 0 V
Serial peripheral interface inputs; pins SDI, SCK and SCS
−25
-
−1.3
μA
V_IH(th)
HIGH-level input
threshold voltage
0.7 × V_V1 -
V_V1 + 0.3 V
V_IL(th)
LOW-level input
threshold voltage
−0.3
-
0.3 × V_V1 V
R_pd(SCK)
pull-down resistor at V_SCK = 2 V; V_V1 ≥ 2 V
pin SCK
50
130
400
kΩ
R_pu(SCS)
pull-up resistor at
pin SCS
V_SCS = 1 V; V_V1 ≥ 2 V
50
130
400
kΩ
I_LI(SDI)
input leakage current V_SDI = 0 V to V_V1
at pin SDI
−5
-
+5
μA
Serial peripheral interface data output; pin SDO
I_OH
HIGH-level output
V_O = V_V1 − 0.4 V; V_SCS = 0 V
−50
-
−1.6
mA
current
I_OL
LOW-level output
V_O = 0.4 V; V_SCS = 0 V
1.6
-
20
mA
current
I_LO(off)
OFF-state output
leakage current
V_O = 0 V to V_V1; V_SCS = V_V1
−5
-
+5
μA
Reset output with clamping detection; pin RSTN
I_OH
HIGH-level output
V_RSTN = 0.7 × V_V1(nom)
−1000 -
−50
μA
current
I_OL
LOW-level output
V_RSTN = 0.9 V
current
1
-
5
mA
V_OL
LOW-level output
V_V1 = 1.5 V to 5.5 V; pull-up
0
-
0.2 × V_V1 V
voltage
resistor to V1 = ≥ 4 kΩ
V_IH(th)
HIGH-level input
threshold voltage
0.7 × V_V1 -
V_V1 + 0.3 V
UJA1061_6
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 06 — 9 March 2010
© NXP B.V. 2010. All rights reserved.
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