UJA1061_10 Datasheet, PDF (49/77 Pages) NXP Semiconductors – Fault-tolerant CAN/LIN fail-safe system basis chip

NXP Semiconductors
UJA1061
Fault-tolerant CAN/LIN fail-safe system basis chip
Table 26. Static characteristics^[1] …continued
T_vj = −40 °C to +150 °C; V_BAT42 = 5.5 V to 52 V;V_BAT14 = 5.5 V to 27 V; V_BAT42 ≥ V_BAT14 − 1 V; unless otherwise specified. All
voltages are defined with respect to ground. Positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
I_thH(V1)
undercurrent
threshold for
watchdog enable
−10
−5
−2
mA
I_thL(V1)
undercurrent
threshold for
watchdog disable
−6
−3
−1.5
mA
I_V1
output current
V_BAT14 = 9 V to 27 V;
−200
−135
−120
mA
capability
δV_V1 = 0.05 × V_V1(nom)
V_BAT14 = 9 V to 27 V;
V1 shorted to GND
−200 −110
-
mA
Z_ds(on)
regulator impedance
between pins BAT14
and V1
V_BAT14 = 8 V to 9 V;
δV_V1 = 0.05 × V_V1(nom)
V_BAT14 = 5.5 V to 8 V;
δV_V1 = 0.05 × V_V1(nom)
V_BAT14 = 4 V to 5 V
-
-
−120
mA
-
-
−150
mA
-
3
5
Ω
Voltage source; pin V2^[4]
V_o(V2)
ΔV_V2
I_V2
output voltage
supply voltage
regulation
load regulation
voltage drift with
temperature
output current
capability
V_BAT14 = 9 V to 16 V;
I_V2 = −50 mA to −5 mA
4.8
5.0
V_BAT14 = 14 V; I_V2 = −10 mA;
T_j = 25 °C
4.95
5.0
V_BAT14 = 9 V to 16 V;
I_V2 = −10 mA; T_j = 25 °C
-
1
V_BAT14 = 14 V; I_V2 = −50 mA
-
-
to −5 mA; T_j = 25 °C
V_BAT14 = 14 V; I_V2 = −10 mA; ^[3] -
-
−40 °C < T_j < 150 °C
V_BAT14 = 9 V to 27 V;
δV_V2 = 300 mV
−200 -
V_BAT14 = 9 V to 27 V; V2
shorted to GND
−300 -
5.2
5.05
25
50
200
−120
-
V
V
mV
mV
ppm/K
mA
mA
V_det(UV)(V2)
V_BAT14 = 6 V to 8 V;
δV_V2 = 300 mV
-
-
−80
mA
V_BAT14 = 5.5 V; δV_V2 = 300 mV
-
-
−50
mA
undervoltage
detection threshold
V_BAT14 = 14 V
4.5
4.6
4.8
V
Voltage source; pin V3
V_{BAT42-V3(drop)}
I_det(OL)(V3)
V_BAT42 to V_V3 voltage
drop
overload current
detection threshold
V_BAT42 = 9 V to 52 V;
I_V3 = −20 mA
V_BAT42 = 9 V to 52 V
-
-
−165 -
1.0
V
−60
mA
UJA1061_6
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 06 — 9 March 2010
© NXP B.V. 2010. All rights reserved.
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