UJA1061_10 Datasheet, PDF (39/77 Pages) NXP Semiconductors – Fault-tolerant CAN/LIN fail-safe system basis chip

NXP Semiconductors
UJA1061
Fault-tolerant CAN/LIN fail-safe system basis chip
[3] In case of an RXDC / TXDC interfacing failure the LIN transmitter is disabled without setting LTC. Recovery from such a failure is
automatic when LIN communication (with correct interfacing levels) is received. Manual recovery is also possible by setting and clearing
the LTC bit under software control.
6.13.10 Special Mode register and Special Mode Feedback register
These registers allow configuration of global SBC parameters during start-up of a system,
and allow the settings to be read back.
Table 13. Special Mode register and Special Mode Feedback register bit description
Bit
Symbol
Description
Value Function
15 and 14 A1, A0
register address
01
select Special Mode register
13
RRS
Read Register Select 0
read the Interrupt Enable Feedback register
1
read the Special Mode Feedback register
12
RO
Read Only
1
read the register selected by RRS without writing to the
Special Mode register
0
read the register selected by RRS and write to the Special
Mode register
11 and 10 -
reserved
0
reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
9
ISDM
Initialize Software
1
initialization of Software Development mode
Development Mode^[1] ₀
normal watchdog interrupt, reset monitoring and fail-safe
behavior
8
ERREM
Error-pin Emulation
1
pin EN reflects the status of the CANFD bits:
Mode
EN is set if CANFD = 0000 (no error)
EN is cleared if CANFD is not 0000 (error)
0
pin EN behaves as an enable pin; see Section 6.5.2
7
-
reserved
0
reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
6 and 5 WDPRE Watchdog Prescaler 00
[1:0]
01
watchdog prescale factor 1
watchdog prescale factor 1.5
10
watchdog prescale factor 2.5
11
watchdog prescale factor 3.5
4 and 3 V1RTHC V1 Reset Threshold
11
[1:0]
Control
10
01
00
2 to 0
-
reserved
0
V1 reset threshold = 0.9 × V_V1(nom)
V1 reset threshold = 0.7 × V_V1(nom)[2]
V1 reset threshold = 0.8 × V_V1(nom)
V1 reset threshold = 0.9 × V_V1(nom)
reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
[1] See Section 6.14.1.
[2] Not supported in the UJA1061TW/3V3 version.
UJA1061_6
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 06 — 9 March 2010
© NXP B.V. 2010. All rights reserved.
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