UJA1061_10 Datasheet, PDF (26/77 Pages) NXP Semiconductors – Fault-tolerant CAN/LIN fail-safe system basis chip

NXP Semiconductors
UJA1061
Fault-tolerant CAN/LIN fail-safe system basis chip
6.8.6.3 LIN recessive clamping
If the LIN bus pin is clamped recessive while TXDL is driven dominant the LIN transmitter
is disabled. The transmitter is reactivated automatically when the LIN bus becomes
dominant or manually by setting and clearing the LTC bit.
6.9 Inhibit and limp-home output
The INH/LIMP output pin is a 3-state output pin which can be used either as an inhibit for
an extra (external) voltage regulator, or as a ‘limp-home’ output. The pin is controlled via
the ILEN bit and ILC bit in the System Configuration register; see Figure 12.
When pin INH/LIMP is used as inhibit output, a pull-down resistor to GND ensures a
default LOW level. The pin can be set to HIGH according to the state diagram.
When pin INH/LIMP is used as limp-home output, a pull-up resistor to V_BAT42 ensures a
default HIGH level. The pin is automatically set to LOW when the SBC enters Fail-safe
mode.
INH / LIMP:
HIGH
ILEN = 1
ILC = 1
state change via SPI
OR enter Fail-safe mode
state change via SPI
INH / LIMP:
LOW
ILEN = 1
ILC = 0
state change via SPI
OR (enter Start-up mode after
wake-up reset, external reset
or V1 undervoltage)
OR enter Restart mode
OR enter Sleep mode
state change via SPI
OR enter Fail-safe mode
state change via SPI
state change via SPI
power-on
INH / LIMP:
floating
ILEN = 0
ILC = 1/0
Fig 12. States of the INH/LIMP pin
001aad 178
6.10 Wake-up input
The WAKE input comparator is triggered by negative edges on pin WAKE. Pin WAKE has
an internal pull-up resistor to BAT42. It can be operated in two sampling modes which are
selected via the WAKE Sample Control bit (WSC):
• Continuous sampling (with an internal clock) if the bit is set
• Sampling synchronized to the cyclic behavior of V3 if the bit is cleared; see Figure 13.
This is to save bias current within the external switches in low-power operation. Two
repetition times are possible, 16 ms and 32 ms.
UJA1061_6
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 06 — 9 March 2010
© NXP B.V. 2010. All rights reserved.
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