DAC1208D650 Datasheet, PDF (49/98 Pages) NXP Semiconductors – Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A interface

NXP Semiconductors
DAC1208D650
2×, 4× or 8× interpolating DAC with JESD204A interface
Table 54. MDS_MISCCNTRL1 register (address 06h) bit description …continued
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
4
MDS_RELOCK
R/W
relock mode
0
no action
1
relock when lockout occurs
3 to 0 MDS_LOCK_DELAY[3:0]
R/W
Fh
number of succeeding 'equal'-detections until lock
Table 55. MDS_ADJDELAY register (address 08h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
6 to 0 MDS_ADJDELAY[6:0]
R
-
actual value adjustment delay
Table 56. MDS_STATUS0 register (address 09h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7
EARLY
R
0
1
6
LATE
R
0
1
5
EQUAL
R
0
1
4
MDS_LOCK
R
0
1
3
EARLY_ERROR
R
0
1
2
LATE_ERROR
R
0
1
1
EQUAL_FOUND
R
0
1
0
MDS_ACTIVE
R
0
1
Description
early signal (sampled) from early-late detector
false
true
late signal (sampled) from early-late detector
false
true
equal signal (sampled) from early-late detector
false
true
result equal check
false
true
adjustment delay maximum value stops the search
false
true
adjustment delay minimum value stops the search
false
true
evaluation logic has detected equal condition
false
true
evaluation logic active
false
true
DAC1208D650
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 14 December 2010
© NXP B.V. 2010. All rights reserved.
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