DAC1208D650 Datasheet, PDF (15/98 Pages) NXP Semiconductors – Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A interface

NXP Semiconductors
DAC1208D650
2×, 4× or 8× interpolating DAC with JESD204A interface
10.2.4 Descrambler
The descrambler is the a 16-bit parallel self-synchronous descrambler based on the
polynomial 1 + x¹⁴ + x¹⁵. This processing can be turned off.
10.2.5 inter-lane alignment
This feature removes strict PCB design skew compensation between the lanes.
10.2.5.1 Single device operation
This module handles the alignment of the four data streams. Because of inter-lane skew
and each PLL per lane concept, these alignment characters may be received at different
times by the receivers. After the synchronization period, the lock signal will be HIGH. This
enables the receipt of K28.3 /A/ characters.The /A/ characters provided in the initial
alignment sequence are used to align the four data streams.
The ILA_CNTRL register’s SEL_ILA[1:0] bits select which K28.3 /A/ symbol triggers the
initial lane alignment:“00” = 1st /A/ symbol, “01” = 2nd /A/ symbol, “10” = 3rd /A/ symbol,
“11” = 4th /A/ symbol; Table 86 on page 61. When all receivers have received their first
selected /A/, they start propagating the received data to the frame assembly module at the
same point in time.
This module can compensate for up to ±7 frame clock period misalignments between the
lanes.
When initial lane alignment is not supported, the manual alignment mode can be used.
After the initial ILA sequence, the lane alignment monitoring starts. If the received user
data contains a K28.3 /A/ symbol:
• its position is compared to the value of the alignment monitor counter
• if two successive K28.3 /A/ symbols have been received at a wrong position, a
realignment takes place
• if the buffers are empty or overflow, this is indicated by the registers
ILA_BUF_ERR_LN0 to ILA_BUF_ERR_LN3
10.2.5.2 Multi-device operation
DAC1208D650 implements a multi-device inter-lane alignment that guarantees a skew of
less than one output period between them.
Two modes are available: master/slave and all slave. Both make use of the MDS_P and
MDS_N pins.
DAC1208D650
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 14 December 2010
© NXP B.V. 2010. All rights reserved.
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