DAC1208D650 Datasheet, PDF (43/98 Pages) NXP Semiconductors – Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A interface

NXP Semiconductors
DAC1208D650
2×, 4× or 8× interpolating DAC with JESD204A interface
Table 30. DAC_B_CFG_1 register (address 0Ch) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
7
DAC_B_PD
R/W
DAC B power
0
on
1
off
6
DAC_B_SLEEP
R/W
DAC B Sleep mode
0
disabled
1
enabled
5 to 0 DAC_B_OFFSET[5:0]
R/W
00h
lower 6 bits for the DAC B offset
Table 31. DAC_B_CFG_2 register (address 0Dh) bit description
Bit
Symbol
Access Value
7 to 6 DAC_B_GAIN_COARSE[1:0]
R/W
1h
5 to 0 DAC_B_GAIN_FINE[5:0]
R/W
00h
Description
least significant 2 bits for the DAC B gain setting for
coarse adjustment
the 6 bits for the DAC B gain setting for fine
adjustment
Table 32. DAC_B_CFG_3 register (address 0Eh) bit description
Bit
Symbol
Access Value Description
7 to 6 DAC_B_GAIN_COARSE[3:2]
R/W
3h
most significant 2 bits for the DAC B gain setting for
coarse adjustment
5 to 0 DAC_B_OFFSET[11:6]
R/W
00h
most significant 6 bits for the DAC B offset
Table 33. DAC_CFG register (address 0Fh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
1
MINUS_3DB
R/W
0
1
0
NOISE_SHAPER
R/W
0
1
Description
NCO gain
unity
−3 dB
noise shaper
disabled
enabled
Table 34. DAC_CURRENT_0 register (address 11h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
3 to 1 DAC_DIG_BIAS[2:0]
R/W
3h
bias current control (see Table 46)
Table 35. DAC_CURRENT_1 register (address 12h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
3 to 1 DAC_MST_BIAS[2:0]
R/W
3h
bias current control (see Table 46)
DAC1208D650
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 14 December 2010
© NXP B.V. 2010. All rights reserved.
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