PCA9663 Datasheet, PDF (45/66 Pages) NXP Semiconductors – Parallel bus to 3 channel Fm+ I2C-bus controller

NXP Semiconductors
PCA9663
Parallel bus to 3 channel Fm+ I²C-bus controller
8.9 I²C-bus timing diagrams
The diagrams Figure 14 and Figure 15 illustrate typical timing diagrams for the PCA9663.
SCL
SDA
INT
7-bit address⁽¹⁾
START
condition
R/W = 0
ACK
from slave receiver
first byte⁽¹⁾
ACK
n byte⁽¹⁾
ACK
interrupt
(after STOP)
STOP
condition
002aaf301
PCA9663 writes data to slave.
(1) 7-bit address + R/W = 0 byte and number of bytes sent = value programmed in Transaction length
register in TRANCONFIG register.
Fig 14. Bus timing diagram; write transactions
SCL
SDA
INT
START
condition
7-bit address
R/W = 1
ACK
from slave
first byte⁽¹⁾
n byte⁽¹⁾
ACK
no ACK
from PCA9663
interrupt
(after STOP)
STOP
condition
002aaf693
PCA9663 reads data from slave.
(1) Number of bytes received = value programmed in the Transaction length register in
TRANCONFIG.
Fig 15. Bus timing diagram; read transactions
PCA9663
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 6 June 2011
© NXP B.V. 2011. All rights reserved.
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