PCA9663 Datasheet, PDF (29/66 Pages) NXP Semiconductors – Parallel bus to 3 channel Fm+ I2C-bus controller

NXP Semiconductors
PCA9663
Parallel bus to 3 channel Fm+ I²C-bus controller
7.5.1.16 PRESET — I²C-bus channel parallel software reset register
Table 28. PRESET - I²C-bus channel parallel software reset register bit description
Address: Channel 0 = CFh; Channel 1 = DFh; Channel 2 = EFh.
Bit Symbol
Description
7:0 PRESET[7:0] Write-only register used during an I²C-bus channel parallel reset command.
PRESET is an 8-bit write-only register. Programming the PRESET register allows the user
to reset each individual PCA9663 channel under software control. The software reset is
achieved by writing two consecutive bytes to this register. The first byte must be A5h while
the second byte must be 5Ah. The writes must be consecutive and the values must match
A5h and 5Ah. If this sequence is not followed as described, the reset is aborted.
The PRESET resets state-machines, registers, and buffer pointers to the default values,
zeroes the TRANCONFIG, SLATABLE, BYTECOUNT, and DATA arrays of the respective
channel and will not reset the entire chip. The parallel bus remains active while a software
reset is active. The user can read the PRESET register to determine when the reset has
completed, PRESET returns all 1s when the reset is active and all 0s when complete.
7.5.2 Global registers
7.5.2.1 CTRLSTATUS — Controller status register
The CTRLSTATUS register reports the status of the controller, including the interrupts
generated by the parallel bus. There are six status bits. When CTRLSTATUS contains
00h, it indicates the idle state and therefore no serial interrupts are requested. The content
of this register is continuously updated during the operation of the controller.
The lower 3 bits represent the channels that have an interrupt request pending. To clear
the individual channel interrupt request, you must read the CHSTATUS register. Bits [5:3]
indicate if a channel is currently active or if it is in the idle state.
Table 29. CTRLSTATUS - Interrupt status register bit description
Address: F0h.
Bit Symbol
Description
7
BE
Buffer Error. A buffer error such as overflow has been detected.
6
-
5
CH2ACT
Channel 2 is active.
4
CH1ACT
Channel 1 is active.
3
CH0ACT
Channel 0 is active.
2
CH2INTP
Channel 2 interrupt pending.
1
CH1INTP
Channel 1 interrupt pending.
0
CH0INTP
Channel 0 interrupt pending.
Remark: A global reset will reset all channels and configuration settings.
BE - Buffer Error bit: This bit indicates that a buffer error has been detected. For
example, a buffer overflow due to the host programming too many bytes will set this bit. A
software or hardware reset is necessary to recover from a buffer error.
PCA9663
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 6 June 2011
© NXP B.V. 2011. All rights reserved.
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