PCA9663 Datasheet, PDF (1/66 Pages) NXP Semiconductors – Parallel bus to 3 channel Fm+ I2C-bus controller

PCA9663
Parallel bus to 3 channel Fm+ I²C-bus controller
Rev. 1 — 6 June 2011
Product data sheet
1. General description
The PCA9663 is an advanced single master mode I²C-bus controller. It is a fourth
generation bus controller designed for data intensive I²C-bus data transfers. It has three
independent I²C-bus channels with data rates up to 1 Mbits/s using the Fast-mode Plus
(Fm+) open-drain topology. Each channel has a generous 4352 byte data buffer which
makes the PCA9663 the ideal companion to any CPU that needs to transmit and receive
large amounts of serial data.
The PCA9663 is a 8-bit parallel-bus to I²C-bus protocol converter. Each channel can be
configured to communicate with up to 64 slaves in one serial sequence with no
intervention from the CPU. The controller also has a sequence loop control feature that
allows it to automatically retransmit a stored sequence.
Its onboard oscillator and PLL allow the controller to generate the clocks for the I²C-bus
and for the interval timer used in sequence looping. This feature greatly reduces CPU
overhead when data refresh is required in fault tolerant applications.
An external trigger input allows data synchronization with external everts. The trigger
signal controls the rate at which a stored sequence is re-transmitted over the I²C-bus.
Error reporting is handled at the transaction level, channel level and controller level with a
simple interrupt tree and interrupt masks allow further customization of interrupt
management.
The controller and parallel bus interfaces run at 3.3 V and the I²C-bus I/Os are 5 V
tolerant with logic levels referenced to a dedicated V_DD(IO) input pin with a range of 3.0 V
to 5.5 V.
2. Features and benefits
 Parallel-bus to I²C-bus protocol converter and interface
 1 Mbit/s and up to 30 mA SCL/SDA I_OL Fast-mode Plus (Fm+) capability
 Internal oscillator trimmed to 1 % accuracy reduces external components
 Individual 4352-byte buffers for the Fm+ channels for a total of 13056 bytes of buffer
space
 Three levels of reset: individual software reset, global software reset, global hardware
RESET pin
 Communicates with up to 64 slaves on each channel in one serial sequence
 Sequence looping with interval timer
 Supports SCL clock stretching
 JTAG port available for boundary scan testing during board manufacturing process
 Trigger input synchronizes serial communication exactly with external events