PCA9663 Datasheet, PDF (16/66 Pages) NXP Semiconductors – Parallel bus to 3 channel Fm+ I2C-bus controller

NXP Semiconductors
PCA9663
Parallel bus to 3 channel Fm+ I²C-bus controller
Table 6. CONTROL register bits STA, STO, STOSEQ operation/behavior
Channel state
(initialization steps)
Next write action by host
Results
FRAMECNT TE STA STO STOSEQ
Idle (reset, TRANCONFIG,
1
SLATABLE, DATA, STA = 0) ₁
00
01
XX
XX
No action.
START transmitted on serial bus followed by
sequence stored in buffer.
Active (reset, load
1
TRANCONFIG, SLATABLE, ₁
DATA, STA = 1
0X 0 X
0X 1 X
No change; cannot write STA while active.
When the STO bit is set, two actions are
possible:
1. If the transaction is a read, a STOP is
sent after the first read byte (NACK sent)
and the byte count is updated.
2. If the transaction is a write, a STOP is
sent after the end of ACK cycle of the
current byte and BYTECNT is updated.
The SD bits will be set.
REFRATE Loop idle (reset,  1
load TRANCONFIG,
1
SLATABLE, DATA STA = 1)^[1]
00
0X
XX
01
No action.
Channel will go immediately to the inactive
state and SD and FLD bits will be set.^[2]
1
0X 1 X
Channel will go immediately to the inactive
state and SD and FLD bits will be set.^[2]
REFRATE Loop active (reset,  1
load, TRANCONFIG,
1
SLATABLE, DATA, STA = 1)
0X 0 0
0X 0 1
No action.
STOP at end of current frame. The SD and
FLD bits will be set.
1
0X 1 X
When the STO bit is set, two actions are
possible:
1. If the transaction is a read, a STOP is
sent after the first read byte (NACK sent)
and the byte count is updated.
2. If the transaction is a write, a STOP is
sent after the end of ACK cycle of the
current byte and BYTECNT is updated.
The SD and FLD bits will be set.
Trigger Loop Idle (reset, load X
TRANCONFIG, SLATABLE, _X
DATA, STA = 1)
10
1X
XX
01
No action.
STOP at end of current frame. The SD and
FLD bits will be set.
X
1X 1 X
When the STO bit is set, two actions are
possible:
1. If the transaction is a read, a STOP is
sent after the first read byte (NACK sent)
and the byte count is updated.
2. If the transaction is a write, a STOP is
sent after the end of ACK cycle of the
current byte and the BYTECNT is
updated.
The SD and FLD bits will be set.
PCA9663
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 6 June 2011
© NXP B.V. 2011. All rights reserved.
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