TDA6650TT Datasheet, PDF (39/54 Pages) NXP Semiconductors – 5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog)

NXP Semiconductors
TDA6650TT; TDA6651TT
5 V mixer/oscillator and low noise PLL synthesizer
signal
50 Ω source
e
V_meas V
50 Ω
RMS
voltmeter
LBIN
or
IFOUTA
MBIN
DUT
27 Ω
spectrum
analyzer
50 Ω
IFOUTB
V_CCA
fce755
Z_i >> 50 Ω → V_i = 2 × V_meas.
V_i = V_meas + 6 dB.
Fig 25. Maximum RF input level without lock-out in low and mid band with asymmetrical
IF output
signal
50 Ω source
A
C
e
V_meas V
50 Ω V_i
HYBRID
RMS
voltmeter
B
D
50 Ω
HBIN1
IFOUTA
DUT
HBIN2
IFOUTB
27 Ω
spectrum
analyzer
50 Ω
V_CCA
fce756
Loss in hybrid = 1 dB.
V_i = V_meas − loss.
Fig 26. Maximum RF input level without lock-out in high band with asymmetrical IF output
12.1 PLL loop stability of measurement circuit
The TDA6650TT; TDA6651TT PLL loop stability is guaranteed in the configuration of
Figure 27, 28, 29 and 30. In this configuration, the external supply source is 30 V
minimum, the pull-up resistor R19 is 15 kΩ and all of the local oscillators are aligned to
operate at a maximum tuning voltage of 26 V. If the configuration is changed, there might
be an impact on the loop stability.
For any other configurations, a stability analysis must be performed. The conventional PLL
AC model used for the stability analysis, is valid provided the external source (DC supply
source or DC-to-DC converter) is able to deliver a minimum current that is equal to the
charge pump current in use.
TDA6650TT_6651TT_5
Product data sheet
Rev. 05 — 10 January 2007
© NXP B.V. 2007. All rights reserved.
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