PMN49EN Datasheet, PDF (3/12 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

NXP Semiconductors
PMN49EN
N-channel TrenchMOS logic level FET
120
P_der
(%)
80
03aa17
120
I_der
(%)
80
03aa25
40
40
0
0
50
100
150
200
T_sp (°C)
P_der = _P----_t--_o--^P-_t-₍--^t2-^o--₅-^t-_°---_C---₎ × 100 %
Fig 1. Normalized total power dissipation as a
function of solder point temperature
0
0
50
100
150
200
T_sp (°C)
I_der = -_I--_D----₍-^I-₂-^D-₅---_°--_C---₎ × 100 %
Fig 2. Normalized continuous drain current as a
function of solder point temperature
10²
I_D
(A)
10
Limit R_DSon = V_DS / I_D
1
DC
10^-1
003aab227
t_p = 10 µ s
100 µs
1 ms
10 ms
100 ms
10^-2
10^-1
1
10
10²
V_DS (V)
T_sp = 25 °C; I_DM is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PMN49EN_1
Product data sheet
Rev. 01 — 13 April 2007
© NXP B.V. 2007. All rights reserved.
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