PHP225_11 Datasheet, PDF (3/11 Pages) NXP Semiconductors – Dual P-channel intermediate level FET

NXP Semiconductors
PHP225
Dual P-channel intermediate level FET
4. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
V_DS
V_GS
V_GSO
I_D
I_DM
P_tot
drain-source voltage
gate-source voltage
gate-source voltage
drain current
peak drain current
total power dissipation
T_j ≥ 25 °C; T_j ≤ 150 °C
open drain
T_sp ≤ 80 °C
T_sp = 25 °C; pulsed
T_amb = 25 °C
T_sp = 80 °C
T_amb = 25 °C
T_stg
storage temperature
T_j
junction temperature
Source-drain diode
I_S
source current
I_SM
peak source current
T_sp ≤ 80 °C
T_sp = 25 °C; pulsed
Min
-
-
-20
-
[1] _-
[2] _-
[3] _-
[4] _-
[5] _-
-65
-
Max Unit
-30 V
-
V
20 V
-2.3 A
-10 A
1
W
2
W
1.3 W
2
W
150 °C
150 °C
-
[1] _-
-1.25 A
-5
A
[1] Pulse width and duty cycle limited by maximum junction temperature.
[2] Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with a thermal resistance from ambient to
tie-point of 90 K/W.
[3] Maximum permissible dissipation per MOS transistor. Both devices may be loaded up to 2 W at the same time.
[4] Maximum permissible dissipation if only one MOS transistor dissipates. Device mounted on printed-circuit board with a thermal
resistance from ambient to tie-point of 90 K/W.
[5] Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with a thermal resistance from ambient to
tie-point of 27.5 K/W.
2.5
P_tot
(W)
2.0
mlb836
1.5
1.0
0.5
0
0
50
100
Fig 1. Power derating curve
150
200
T_s (°C)
−10²
I_D
(A)
−10
(1)
−1
P
−10^−1
δ = ^tp
T
−10_−^−2_10−1
t_p
T
t
−1
Fig 2. SOAR; P-channel
mbe155
t_p =
10 μs
1 ms
DC
0.1 s
−10 _{VDS (V)} −10²
PHP225
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 4 January 2011
© NXP B.V. 2011. All rights reserved.
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