PHP225_11 Datasheet, PDF (1/11 Pages) NXP Semiconductors – Dual P-channel intermediate level FET

PHP225
Dual P-channel intermediate level FET
Rev. 03 — 4 January 2011
Product data sheet
1. Product profile
1.1 General description
Dual intermediate level P-channel enhancement mode Field-Effect Transistor (FET) in a
plastic package using vertical D-MOS technology. This product is designed and qualified
for use in computing, communications, consumer and industrial applications only.
1.2 Features and benefits
„ Low conduction losses due to low
on-state resistance
„ Suitable for high frequency
applications due to fast switching
characteristics
1.3 Applications
„ Motor and actuator drivers
„ Power management
„ Synchronized rectification
1.4 Quick reference data
Table 1. Quick reference data
Symbol Parameter
V_DS
drain-source voltage
I_D
drain current
P_tot
total power dissipation
Static characteristics
R_DSon
drain-source on-state
resistance
Dynamic characteristics
Q_GD
gate-drain charge
Conditions
T_j ≥ 25 °C; T_j ≤ 150 °C
T_sp ≤ 80 °C
T_sp = 80 °C
Min Typ Max Unit
-
-
-30 V
-
-
-2.3 A
[1] _-
-
2W
V_GS = -10 V; I_D = -1 A;
T_j = 25 °C
-
0.22 0.25 Ω
V_GS = -10 V; I_D = -2.3 A;
V_DS = -15 V; T_j = 25 °C
-
3-
nC
[1] Maximum permissible dissipation per MOS transistor. Both devices may be loaded up to 2 W at the same
time.