ICM7555IN Datasheet, PDF (3/22 Pages) NXP Semiconductors – General purpose CMOS timer

NXP Semiconductors
6. Pinning information
6.1 Pinning
ICM7555
General purpose CMOS timer
GND 1
TRIGGER 2
OUTPUT 3
RESET 4
8 V_DD
ICM7555CD ^{7 DISCHARGE}
ICM7555ID _{6 THRESHOLD}
5 CONTROL_VOLTAGE
002aae400
Fig 2. Pin configuration for SO8
GND 1
8 V_DD
TRIGGER 2 _ICM7555CN 7 DISCHARGE
OUTPUT 3 ^ICM7555IN 6 THRESHOLD
RESET 4
5 CONTROL_VOLTAGE
002aae401
Fig 3. Pin configuration for DIP8
6.2 Pin description
Table 2. Pin description
Symbol
Pin
GND
1
TRIGGER
2
OUTPUT
3
RESET
4
CONTROL_VOLTAGE 5
THRESHOLD
6
DISCHARGE
7
V_DD
8
Description
supply ground
start timer input; (active LOW)
timer logic level output
timer inhibit input; (active LOW)
timing capacitor upper voltage sense input
timing capacitor lower voltage sense input
timing capacitor discharge output
supply voltage
7. Functional description
Refer to Figure 1 “Functional diagram”.
7.1 Function selection
Table 3. Function selection
THRESHOLD voltage TRIGGER voltage
don’t care
don’t care
> ²â„₃ V+
V_th < ²â„₃ V+
don’t care
> ¹â„₃ V+
V_trig > ¹â„₃ V+
< ¹â„₃ V+
RESET^[1]
L
H
H
H
OUTPUT
L
L
stable
H
Discharge switch
on
on
stable
off
[1] RESET will dominate all other inputs; TRIGGER will dominate over THRESHOLD.
ICM7555_2
Product data sheet
Rev. 02 — 3 August 2009
© NXP B.V. 2009. All rights reserved.
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