ICM7555IN Datasheet, PDF (13/22 Pages) NXP Semiconductors – General purpose CMOS timer

NXP Semiconductors
ICM7555
General purpose CMOS timer
V_DD
1 _GND
2 _TRIGGER
V_DD ⁸
RA
DISCHARGE ⁷
3 _OUTPUT
THRESHOLD ⁶
4 _{RESET CONTROL_VOLTAGE} 5
optional
capacitor
C
V_DD ≤ 18 V; t = 1.05 R_AC
Fig 16. Monostable operation
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11.6 Control voltage
The CONTROL_VOLTAGE terminal permits the two trip voltages for the THRESHOLD
and TRIGGER internal comparators to be controlled. This provides the possibility of
oscillation frequency modulation in the astable mode, or even inhibition of oscillation,
depending on the applied voltage. In the monostable mode, delay times can be changed
by varying the applied voltage to the CONTROL_VOLTAGE pin.
11.7 RESET
The RESET terminal is designed to have essentially the same trip voltage as the standard
NE/SE555 device, i.e., 0.6 V to 0.7 V. At all supply voltages it represents an extremely
high input impedance. The mode of operation of the RESET function is, however, much
improved over the standard NE/SE555 device in that it controls only the internal flip-flop,
which in turn controls simultaneously the state of the OUTPUT and DISCHARGE pins.
This avoids the multiple threshold problems sometimes encountered with slow falling
edges in the NE/SE555 devices.
ICM7555_2
Product data sheet
Rev. 02 — 3 August 2009
© NXP B.V. 2009. All rights reserved.
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