TDA8594 Datasheet, PDF (20/48 Pages) NXP Semiconductors – I2C-bus controlled 4 X 50 W power amplifier

NXP Semiconductors
TDA8594
I²C-bus controlled 4 × 50 W power amplifier
I²C-BUS WRITE
SCL
1
2
7
8
9
1
2
7
8
9
SDA
MSB MSB − 1
LSB + 1
ACK MSB MSB − 1
LSB + 1 LSB ACK
S
ADDRESS
I²C-BUS READ
SCL
1
2
W
A
WRITE DATA
A
P
To stop the transfer, after the last acknowledge (A)
a STOP condition (P) must be generated
7
8
9
1
2
7
8
9
SDA
MSB MSB − 1
LSB + 1
ACK MSB MSB − 1
LSB + 1 LSB ACK
S
ADDRESS
R
A
: generated by master (microcontroller)
: generated by slave
S : START
P : STOP
A : acknowledge
NA : not acknowledge
R/W : read / write
Fig 16. I²C-bus read and write modes
READ DATA
NA
P
To stop the transfer, the last byte must not be acknowledged
and a STOP condition (P) must be generated
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8.1 Instruction bytes
I²C-bus mode:
• If bit R/W = 0, the TDA8594 expects three instruction bytes; IB1, IB2 and IB3
• After a power-on reset, all instruction bits are set to zero.
Legacy mode:
• All bits equal to zero define the setting, with the exception of bit IB1[D0] which is
ignored; see Table 8.
Table 8.
Bit
D7
D6
D5
Instruction byte IB1
Description
don’t care
channel 3 clip information on DIAG or STB pin
0 = clip information on DIAG pin
1 = clip information on STB pin
channel 1 clip information on DIAG or STB pin
0 = clip information on DIAG pin
1 = clip information on STB pin
TDA8594_2
Product data sheet
Rev. 02 — 11 December 2007
© NXP B.V. 2007. All rights reserved.
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