TDA8594 Datasheet, PDF (16/48 Pages) NXP Semiconductors – I2C-bus controlled 4 X 50 W power amplifier

NXP Semiconductors
TDA8594
I²C-bus controlled 4 × 50 W power amplifier
Table 4. Diagnostic information availability …continued
Diagnostic information I²C-bus mode
DIAG pin
STB pin
Offset detection
no
no
Load detection
no
no
Overvoltage
yes
no
Legacy mode
DIAG pin
no
no
yes
7.14 Offset detection
The offset detection can be performed with no input signal (for instance when the digital
signal processor is in mute after a start-up) or with an input signal. In I²C-bus mode, if an
I²C-bus read of the output offset is performed, the I²C-bus latches DBx[D2] will be set.
When the amplifier BTL output voltage is within a window with a threshold of 1.75 V
typical, the latches DBx[D2] are reset and setting is disabled. If, for instance, after 1
second an I²C-bus read is performed again and the offset bits are still set, the output has
not crossed the offset threshold during the last 1 second (see Figure 11). This can mean
the applied frequency is below 1 Hz (I²C-bus read interval = 1 s) or an output offset of
more than 1.75 V is present.
I²C-bus mode only
V_O = V_OUT+ − V_OUT−
offset
threshold
reset:
setting
disabled
t
t = 1 s:
read = no offset
DB1 bit D2 reset
V_O = V_OUT+ − V_OUT−
offset
threshold
read = set bit
Fig 11. Offset detection
t
t = 1 s:
read = offset
DB1 bit D2 set
001aad175
7.15 DC load detection
When the DC load detection is enabled with IB1[D1], a DC offset is slowly applied at the
output of the amplifiers during the start-up cycle and the load currents are measured.
Different load levels will be detected to differentiate between normal load, line driver load
or open load.
TDA8594_2
Product data sheet
Rev. 02 — 11 December 2007
© NXP B.V. 2007. All rights reserved.
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