BUK7230-55A Datasheet, PDF (2/13 Pages) NXP Semiconductors – TrenchMOS standard level FET

NXP Semiconductors
BUK7230-55A
N-channel TrenchMOS standard level FET
2. Pinning information
Table 2. Pinning information
Pin
Symbol Description
1
G
gate
2
D
drain
3
S
source
mb
D
mounting base; connected to
drain
3. Ordering information
Simplified outline
mb
2
1
3
SOT428 (DPAK)
Graphic symbol
D
G
mbb076 S
Table 3. Ordering information
Type number
Package
Name
Description
BUK7230-55A DPAK
plastic single-ended surface-mounted package (DPAK); 3 leads (one
lead cropped)
4. Limiting values
Version
SOT428
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min Max Unit
V_DS
V_DGR
V_GS
I_D
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
I_DM
peak drain current
P_tot
total power dissipation
T_stg
storage temperature
T_j
junction temperature
Source-drain diode
T_j ≥ 25 °C; T_j ≤ 175 °C
R_GS = 20 kΩ
T_mb = 25 °C; V_GS = 5 V; see Figure 1 and 3
T_mb = 100 °C; V_GS = 5 V; see Figure 1
T_mb = 25 °C; t_p ≤ 10 µs; pulsed; see Figure 3
T_mb = 25 °C; see Figure 2
-
55
V
-
55
V
-20 20
V
-
38
A
-
27
A
[1]
-
150 A
-
88
W
-55 175 °C
-55 175 °C
I_S
source current
I_SM
peak source current
Avalanche ruggedness
T_mb = 25 °C
t_p ≤ 10 µs; pulsed; T_mb = 25 °C
-
38
A
-
150 A
E_DS(AL)S
non-repetitive
I_D = 34 A; V_sup ≤ 55 V; R_GS = 50 Ω; V_GS = 10 V;
drain-source avalanche T_j(init) = 25 °C; unclamped
energy
-
58
mJ
[1] Peak drain current is limited by chip, not package.
BUK7230-55A_2
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 16 March 2010
© NXP B.V. 2010. All rights reserved.
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