74HC74D-T Datasheet, PDF (12/22 Pages) NXP Semiconductors – Dual D-type flip-flop with set and reset; positive-edge trigger

Philips Semiconductors
Dual D-type flip-flop with set and reset;
positive-edge trigger
Product specification
74HC74; 74HCT74
Family 74HCT
GND = 0 V; t_r = t_f = 6 ns; C_L = 50 pF.
SYMBOL
PARAMETER
TEST CONDITIONS
WAVEFORMS
V_CC (V)
MIN.
T_amb = −40 to +85 °C
t_PHL/t_PLH
propagation
see Fig.7
delay nCP to nQ, nQ
propagation
see Fig.8
delay nSD to nQ, nQ
propagation
see Fig.8
delay nRD to nQ, nQ
t_THL/t_TLH
t_W
output transition time see Fig.7
clock pulse width HIGH see Fig.7
or LOW
set or reset pulse width see Fig.8
LOW
t_rem
removal time set or
see Fig.8
reset
t_su
set-up time nD to nCP see Fig.7
t_h
hold time nCP to nD see Fig.7
f_max
maximum clock pulse see Fig.7
frequency
4.5
−
4.5
−
4.5
−
4.5
−
4.5
23
4.5
20
4.5
8
4.5
15
4.5
+3
4.5
22
T_amb = −40 to +125 °C
t_PHL/t_PLH
propagation
see Fig.7
delay nCP to nQ, nQ
propagation
see Fig.8
delay nSD to nQ, nQ
propagation
see Fig.8
delay nRD to nQ, nQ
t_THL/t_TLH
t_W
output transition time see Fig.7
clock pulse width HIGH see Fig.7
or LOW
set or reset pulse width see Fig.8
LOW
t_rem
removal time set or
see Fig.8
reset
t_su
set-up time nD to nCP see Fig.7
t_h
hold time nCP to nD see Fig.7
f_max
maximum clock pulse see Fig.7
frequency
4.5
−
4.5
−
4.5
−
4.5
−
4.5
27
4.5
24
4.5
9
4.5
18
4.5
3
4.5
18
TYP.
18
23
24
7
9
9
1
5
−3
54
−
−
−
−
−
−
−
−
−
−
MAX.
44
50
50
19
−
−
−
−
−
−
53
60
60
22
−
−
−
−
−
−
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
2003 Jul 10
12