GTL2005 Datasheet, PDF (1/19 Pages) NXP Semiconductors – Quad GTL/GTL to LVTTL/TTL bidirectional non-latched translator

GTL2005
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched
translator
Rev. 07 — 3 February 2009
Product data sheet
1. General description
The GTL2005 is a quad translating transceiver designed for 3.3 V system interface with a
GTL/GTL+ bus.
The direction pin (DIR) allows the part to function as either a GTL-to-TTL sampling
receiver or as a TTL-to-GTL interface.
The GTL2005 LVTTL interface is tolerant up to 5.5 V allowing direct access to TTL or 5 V
CMOS outputs.
The GTL2005 V_ref linearity degrades below 0.8 V (see Section 10.1). If the application
allows, use the GTL2014, otherwise more closely review noise margins.
fast t_PD
GTL2005
slow t_PD
GTL−
GTL2014
GTL
Fig 1. GTL2005/GTL2014 positioning
GTL+
002aab378
2. Features
I Operates as a quad GTL/GTL+ sampling receiver or as a LVTTL/TTL to GTL/GTL+
driver
I Quad bidirectional bus interface
I 3.0 V to 3.6 V operation with 5 V tolerant LVTTL I/O
I Live insertion/extraction permitted
I Latch-up protection exceeds 500 mA per JESD78
I ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per
JESD22-A115, and 1000 V CDM per JESD22-CC101
I Package offered: TSSOP14