DS92LV1260 Datasheet, PDF (9/17 Pages) National Semiconductor (TI) – Six Channel 10 Bit BLVDS Deserializer

Data Transfer (Continued)
The Deserializer input pins are high impedance during Pow-
erdown (PWRDN low) and power-off (V_cc = 0V).
Resynchronization
Whenever one of the six Deserializers loses lock, it will
automatically try to resynchronize. For example, if the em-
bedded clock edge is not detected two times in succession,
the PLL loses lock and the LOCKn pin is driven high. The
system must monitor the LOCKn pin to determine when data
is valid.
The user has the choice of allowing the deserializer to re-
synch to the data stream or to force synchronization by
pulsing the Serializer SYNC1 or SYNC2 pin. This scheme is
left up to the user discretion. One recommendation is to
provide a feedback loop using the LOCKn pin itself to control
the sync request of the Serializer (SYNC1 or SYNC2). Dual
SYNC pins are given for multiple control in a multi-drop
application.
Powerdown
The Powerdown state is a low power sleep mode that the
Serializer and Deserializer typically occupy while waiting for
initialization, or to reduce power consumption when no data
is transfers. The Deserializer enters Powerdown when
PWRDN is driven low. In Powerdown, the PLL stops and the
outputs go into TRI-STATE, which reduces supply current to
the microamp range. To exit Powerdown, the system drives
PWRDN high.
Upon exiting Powerdown, the Deserializer enters the Initial-
ization state. The system must then allow time to Initialize
before data transfer can begin.
TRI-STATE
When the system drives REN pin low, the Deserializer enters
TRI-STATE. This will TRI-STATE the receiver output pins
(ROUT[00:59]) and RCLK[0:5]. When the system drives
REN high, the Deserializer will return to the previous state as
long as all other control pins remain static (PWRDN,
RCLK_R/F).
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