DS92LV1260 Datasheet, PDF (1/17 Pages) National Semiconductor (TI) – Six Channel 10 Bit BLVDS Deserializer

August 2003
DS92LV1260
Six Channel 10 Bit BLVDS Deserializer
General Description
The DS92LV1260 integrates six deserializer devices into a
single chip. The chip uses a 0.25u CMOS process technol-
ogy. The DS92LV1260 can simultaneously deserialize up to
six data streams that have been serialized by the National
Semiconductor DS92LV1021 or DS92LV1023 Bus LVDS se-
rializers. The device also includes a seventh serial input
channel that serves as a redundant input.
Each deserializer block in the DS92LV1260 operates inde-
pendently with its own clock recovery circuitry and lock-
detect signaling.
The DS92LV1260 uses a single +3.3V power supply with a
typical power dissipation of 1.2W at 3.3V with a PRBS-15
pattern. Refer to the Connection Diagrams for packaging
information.
Features
n Deserializes one to six BusLVDS input serial data
streams with embedded clocks
n Seven selectable serial inputs to support n+1
redundancy of deserialized streams
n Seventh channel has single pin monitor output that
reflects input from seventh channel input
n Parallel clock rate up to 40MHz
n On chip filtering for PLL
n Absolute maximum worst case power dissipation =
1.9W at 3.6V
n High impedance inputs upon power off (V_cc = 0V)
n Single power supply at +3.3V
n 196-pin LBGA package (Low-profile Ball Grid Array)
package
n Industrial temperature range operation: −40˚C to +85˚C
Block Diagram
Application
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