DS92LV1260 Datasheet, PDF (15/17 Pages) National Semiconductor (TI) – Six Channel 10 Bit BLVDS Deserializer

Pin Descriptions
Pins
B2,B14
Pin Name
GND
C12,C13,B13
SEL (0:2)
A4-A3, C6-C5, A7-A6,
C9-C8, A10-A9,
C11-C10, A13-A12
D12
F12
B12,A14,D10
B11
C7
B9
A11
B7
A8
B8
A5
B6
D7
Rin(n) +/-
PVdd
AVdd
PGND
AGND
AVdd
AVdd
AVdd
AGND
AGND
AGND
AGND
AVdd
DGND
B5
PWRDN
C4
RCLK_R/F
A2
REN
B4
REFCLK
D5
DGND
A1
DGND
B1
N/C
D6
DVdd
B3
DVdd
C3
CHTST
F3,P1,N3,P12,P13,D13
E6,J5,K5,K10,J10,E9
LOCK (0:5)
DVdd
Type
GND
3.3V
CMOS
I
Bus
LVDS
I
3.3V
CMOS
I
3.3V
CMOS
I
3.3V
CMOS
I
3.3V
CMOS
I
3.3V
CMOS
O
3.3V
CMOS
O
Description
GND pins for ESD structures
These pins control which Bus LVDS input is steered to the
CHTST output
Bus LVDS differential input pins
Supply voltage for PLL circuitry
Supply voltage for input buffer circuitry
GND pin for PLL circuitry
GND pin for input buffer circuitry
Supply voltage for LVDS REC.
Supply voltage for LVDS REC.
Supply voltage for Band Gap reference.
GND pin for AVDD.
GND pin for AVDD1.
GND pin for BGVDD.
GND pin for VDDI.
Supply voltage for input logic circuitry.
Tie to digital ground.
Controls whether the device is active or in ’sleep’ mode
Controls the relation of Rout data to RCLK edge: RCLK_R/F
= H setup and hold times are referred to the rising RCLK
edge; RCLK_R/F = L setup and hold times are referenced to
the falling RCLK edge.
Enables the Routn, RCLKn, and SYNCCLK outputs.
Frequency reference clock input.
GND pin for VDDO
GND for digital section.
Do not connect.
Supply voltage for digital section.
Supply voltage for digital section.
Allows low speed testing of the Rin inputs under control of
the SEL (0:2) pins.
Indicates the status of the PLLs for the individual
deserializers: LOCK= L indicates locked, LOCK= H indicates
unlicked.
Supply voltage for the logic circuitry.
15
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