DS92LV1260 Datasheet, PDF (10/17 Pages) National Semiconductor (TI) – Six Channel 10 Bit BLVDS Deserializer

Application Information
USING THE DS92LV1021 AND DS92LV1260
The DS92LV1260 combines six 1:10 deserializers into a
single chip. Each of the six deserializers accepts a BusLVDS
data stream up to 480 Mbps from National Semiconductor’s
DS92LV1021 or DS92LV1023 Serializer. The deserializers
then recover the embedded two clock bits and data to deliver
the resulting 10-bit wide words to the output. A seventh serial
data input provides n+1 redundancy capability. The user can
program the seventh input to be an alternative input to any of
the six deserializers. Whichever input is replaced by the
seventh input is then routed to the CHANNEL TEST
(CHTST) pin on receiver output port. The Deserializer uses a
separate reference clock (REFCLK) and an onboard PLL to
extract the clock information from the incoming data stream
and then deserialize the data. The Deserializer monitors the
incoming clock information, determines lock status, and as-
serts the LOCKn output high when loss of lock occurs.
POWER CONSIDERATIONS
An all CMOS design of the Deserializer makes it an inher-
ently low power device.
POWERING UP THE DESERIALIZER
The DS92LV1260 can be powered up at any time by follow-
ing the proper sequence. The REFCLK input can be running
before the Deserializer powers up, and it must be running in
order for the Deserializer to lock to incoming data. The
Deserializer outputs will remain in TRI-STATE until the De-
serializer detects data transmission at its inputs and locks to
the incoming data stream.
TRANSMITTING DATA
Once you power up the Deserializer, it must be phase locked
to the transmitter to transmit data. Phase locking occurs
when the Deserializer locks to incoming data or when the
Serializer sends sync patterns. The Serializer sends SYNC
patterns whenever the SYNC1 or SYNC2 inputs are high.
The LOCKn output of the Deserializer remains high until it
has locked to the incoming data stream. Connecting the
LOCKn output of the Deserializer to one of the SYNC inputs
of the Serializer will guarantee that enough SYNC patterns
are sent to achieve Deserializer lock.
The Deserializer can also lock to incoming data by simply
powering up the device and allowing the “random lock”
circuitry to find and lock to the data stream.
NOISE MARGIN
While the Deserializer LOCKn output is low, data at the
Deserializer outputs (ROUT0-9) are valid, except for the
specific case of loss of lock during transmission which is
further discussed in the "Recovering from LOCK Loss" sec-
tion below.
The Deserializer noise margin is the amount of input jitter
(phase noise) that the Deserializer can tolerate and still
reliably receive data. Various environmental and systematic
factors include:
Serializer: TCLK jitter, V_CC noise (noise bandwidth and
out-of-band noise)
Media: ISI, Large V_CM shifts
Deserializer: V_CC noise
RECOVERING FROM LOCK LOSS
In the case where the Deserializer loses lock during data
transmission, up to 1 cycle of data that was previously
received can be invalid. This is due to the delay in the lock
detection circuit. The lock detect circuit requires that invalid
clock information be received 2 times in a row to indicate
loss of lock. Since clock information has been lost, it is
possible that data was also lost during these cycles. There-
fore, after the Deserializer relocks to the incoming data
stream and the Deserializer LOCKn pin goes low, at least
one previous data cycle should be suspect for bit errors.
The Deserializer can relock to the incoming data stream by
making the Serializer resend SYNC patterns, as described
above, or by random locking, which can take more time,
depending on the data patterns being received.
HOT INSERTION
All the BusLVDS devices are hot pluggable if you follow a
few rules. When inserting, ensure the Ground pin(s) makes
contact first, then the VCC pin(s), and then the I/O pins.
When removing, the I/O pins should be unplugged first, then
the VCC, then the Ground. Random lock hot insertion is
illustrated in Figure 11.
TRANSMISSION MEDIA
The Serializer and Deserializer can also be used in point-to-
point configurations, through PCB trace, or through twisted
pair cable. In point-to-point configurations, the transmission
media need only be terminated at the receiver end. Please
note that in point-to-point configurations, the potential of
offsetting the ground levels of the Serializer vs. the Deseri-
alizer must be considered. Also, Bus LVDS provides a +/−
1V common mode range at the receiver inputs.
FAILSAFE BIASING FOR THE DS92LV1260
The DS92LV1260 has internal failsafe biasing and an im-
proved input threshold sensitivity of +/− 50mV versus +/−
100mV for the DS92LV1210 or DS92LV1212. This allows for
greater differential noise margin in the DS92LV1260. How-
ever, in cases where the receiver input is not being actively
driven, the increased sensitivity of the DS92LV1260 can
pickup noise as a signal and cause unintentional locking .
For example, this can occur when the input cable is discon-
nected.
External resistors can be added to the receiver circuit board
to prevent noise pick-up. Typically, the non-inverting receiver
input is pulled up and the inverting receiver input is pulled
down by high value resistors. The pull-up and pull-down
resistors (R₁ and R₂) provide a current path through the
termination resistor (R_L) which biases the receiver inputs
when they are not connected to an active driver. The value of
the pull-up and pull-down resistors should be chosen so that
enough current is drawn to provide a +15mV drop across the
termination resistor. Please see Figure 9 for the Failsafe
Biasing Setup.
PCB LAYOUT AND POWER SYSTEM
CONSIDERATIONS
Circuit board layout and stack-up for the DS92LV1260
should be designed to provide noise-free power to the de-
vice. Good layout practice will separate high frequency or
high level inputs and outputs to minimize unwanted stray
noise pickup, feedback and interference. There are a few
common practices which should be followed when designing
PCB’s for Bus LVDS Signaling. Recommended layout prac-
tices are:
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