DS92LV1260 Datasheet, PDF (3/17 Pages) National Semiconductor (TI) – Six Channel 10 Bit BLVDS Deserializer

Electrical Characteristics (Continued)
Basic functionality and specifications per deserializer channel will be similar to National Semiconductor’s DS92LV1212A.
Over recommended operating supply and termperature ranges unless otherwise specified.(Note 2)
Symbol
Parameter
Conditions Pin/Freq.
Min
Typ
Max
Units
t_RFTT
REFCLK Transition Time
Deserializer Switching Characteristics
8
ns
t_RCP
t_RDC
RCLK Period
RCLK Duty Cycle
25
62.5
ns
RCLK
43
50
55
%
Period of Bus LVDS signal
t_CHTST
when CHTST is selected by
(Note 7)
CHTST
25
ns
MUX
CMOS/TTL Low-to-High
t_CLH
Transition Time
1.7
6
ns
CMOS/TTL High-to-Low
t_CHL
Transition Time
1.6
6
ns
Rout Data Valid before
t_ROS
RCLK
Figure 2
0.4*t_RCP
ns
Rout,
t_ROH
Rout Data Valid after RCLK
Figure 2
LOCK,
-0.4*t_RCP
ns
RCLK
t_HZR
High to TRI-STATE Delay
10
ns
t_LZR
Low to TRI-STATE Delay
10
ns
t_ZHR
TRI-STATE to High Delay
12
ns
t_ZLR
TRI-STATE to Low Delay
12
ns
Figure 1
RCLK
1.75*t_RCP+5 1.75*t_RCP+7 1.75*t_RCP+10 ns
t_DD
Deserializer Delay
Room Temp
3.3V
1.75*t_RCP+6 1.75*t_RCP+7 1.75*t_RCP+9
ns
40MHz
t_DSR1
Deserializer PLL LOCK Time
from PWRDN (with
SYNCPAT)
Figure 3
(Note 5)
40MHz
20MHz
3
us
10
us
t_DSR2
Deserializer PLL Lock Time
from SYNCPAT
Figure 4
(Note 5)
40MHz
20MHz
2
us
5
us
40MHz
450
920
ps
t_RNM
Deserializer Noise Margin
(Note 6)
20MHz
1200
1960
ps
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Typical values are given for Vcc = 3.3V and TA =25˚C
Note 3: Current into the device pins is defined as positive. Current out of device pins is defined as negative. Voltage are referenced to ground except VTH and VTL
which are differential voltages.
Note 4: Only one output should be shorted at a time. Do not exceed maximum package power dissipation capacity.
Note 5: For the purpose of specifying deserializer PLL performance t_DSR1 and t_DSR2 are specified with the REFCLK running and stable, and specific conditions of
the incoming data stream (SYNCPATs). t_DSR1 is the time required for the deserializer to indicate lock upon power-up or when leaving the power-down mode. t_DSR2
is the time required to indicate lock for the powered-up and enabled deserializer when the input (RI+ and RI−) conditions change from not receiving data to receiving
synchronization patterns (SYNCPATs). The time to lock to random data is dependent upon the incoming data.
Note 6: t_RNM is a measure of how much phase noise (jitter)the deserializer can tolerate in the incoming data stream before bit errors occur. The Deserializer Noise
Margin is Guaranteed By Design (GBD) using statistical analysis.
Note 7: Because the Bus LVDS serial data stream is not decoded, the maximum frequency of the CHTST output driver could be exceeded if the data stream were
switched to CHTST. The maximum frequency of the BUS LVDS input should not exceed the parallel clock rate.
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