DS92LV1021A Datasheet, PDF (9/12 Pages) National Semiconductor (TI) – 16-40 MHz 10 Bit Bus LVDS Serializer

AC Timing Diagrams and Test Circuits (Continued)
For an explanation of the Ideal Crossing Point, please see the Application Information Section.
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FIGURE 9. Serializer Deterministic Jitter and Ideal Crossing Point
Application Information
DIFFERENCES BETWEEN THE DS92LV1021A AND THE
DS92LV1021
The DS92LV1021A is an enhanced version of the
DS92LV1021. The following enhancements are provided by
the DS92LV1021A:
• TCLK may be applied before power
• TCLK may be halted
• Slower typical edge rates help to reduce reflections
• PWRDN pin includes an internal weak pull down device
Like the DS92LV1021, the DS92LV1021A is a 10-bit Serial-
izer designed to transmit data over a differential backplane
at clock speeds from 16 to 40MHz. It may also be used to
drive data over Unshielded Twisted Pair (UTP) cable.
USING THE DS92LV1021A
The Serializer is an easy to use transmitter that sends 10 bits
of parallel TTL data over a serial Bus LVDS link up to 400
Mbps. Serialization of the input data is accomplished using
an onboard PLL which embeds two clock bits with the data.
POWER CONSIDERATIONS
An all CMOS design of the Serializer makes it an inherently
low power device. Additionally, the constant current source
nature of the Bus LVDS outputs minimize the slope of the
speed vs. I_CC curve of CMOS designs.
DIGITAL AND ANALOG POWER PINS
Digital and Analog power supply pins should be at the same
voltage levels. The user should verify that voltage levels at
the digital and analog supply pins are at the same voltage
levels after board layout and after bypass capacitors are
added.
HOT INSERTION
All Bus LVDS devices are hot pluggable if you follow a few
rules. When inserting, ensure the Ground pin(s) makes con-
tact first, then the VCC pin(s), and then the I/O pins. When
removing, the I/O pins should be unplugged first, then the
VCC, then the Ground.
TRANSMITTING DATA
Once the Serializer and Deserializer are powered up and
running they must be phase locked to each other in order to
transmit data. Phase locking can be accomplished by the
Serializer sending SYNC patterns to the Deserializer, or by
using the Deserializer’s random lock capability. SYNC pat-
terns are sent by the Serializer whenever SYNC1 or SYNC2
inputs are held high. The LOCK output of the Deserializer is
high whenever the Deserializer is not locked. Connecting the
LOCK output of the Deserializer to one of the SYNC inputs of
the Serializer will guarantee that enough SYNC patterns are
sent to achieve Deserializer lock.
While the Deserializer LOCK output is low, data at the De-
serializer outputs (ROUT0-9) is valid except for the specific
case of loss of lock during transmission.
RECOVERING FROM LOCK LOSS
In the case where the Serializer loses lock during data
transmission up to three cycles of data that was previously
received can be invalid. This is due to the delay in the lock
detection circuit. The lock detect circuit requires that invalid
clock information be received 4 times in a row to indicate
loss of lock. Since clock information has been lost it is
possible that data was also lost during these cycles. When
the Deserializer LOCK pin goes low, data from at least the
previous three cycles should be resent upon regaining lock.
Lock can be regained at the Deserializer by causing the
Serializer to resend SYNC patterns as described above.
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