DS92LV1021A Datasheet, PDF (5/12 Pages) National Semiconductor (TI) – 16-40 MHz 10 Bit Bus LVDS Serializer

Serializer Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
t_TCP
t_TCIH
t_TCIL
t_CLKT
Transmit Clock Period
Transmit Clock High Time
Transmit Clock Low Time
TCLK Input Transition
Time
25
0.4T
0.4T
T
0.5T
0.5T
3
t_JIT
TCLK Input Jitter
Max
62.5
0.6T
0.6T
6
150
Units
ns
ns
ns
ns
ps
(RMS)
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
t_LLHT
t_LHLT
Bus LVDS
Low-to-High
Transition Time
Bus LVDS
High-to-Low
Transition Time
R_L = 27Ω,
Figure 2,
C_L=10pF to GND
0.31
0.30
t_DIS
DIN (0-9) Setup to
TCLK
t_DIH
DIN (0-9) Hold from
TCLK
t_HZD
DO ± HIGH to
TRI-STATE Delay
t_LZD
DO ± LOW to
TRI-STATE Delay
t_ZHD
DO ± TRI-STATE to
HIGH Delay
t_ZLD
DO ± TRI-STATE to
LOW Delay
Figure 4,
R_L = 27Ω,
C_L=10pF to GND
Figure 5 ,(Note 4),
R_L = 27Ω,
C_L=10pF to GND
0
4.0
3.5
2.9
2.5
2.7
t_SPW
t_PLD
t_SD
t_BIT
t_DJIT
SYNC Pulse Width
Serializer PLL Lock
Time
Serializer Delay
Bus LVDS Bit Width
Deterministic Jitter
Figure 7,
R_L = 27Ω
Figure 6,
R_L = 27Ω
Figure 8 , R_L = 27Ω
R_L = 27Ω,
C_L=10pF to GND
R_L = 27Ω,
C_L=10pF to GND,
(Note 5)
f = 40 MHz
f = 16 MHz
5*t_TCP
510*t_TCP
t_TCP+1.0
−320
−800
t_TCP + 2.0
t_CLK / 12
−110
−160
Max
Units
0.75
ns
0.75
ns
ns
ns
10
ns
10
ns
10
ns
10
ns
ns
2049*t_TCP
ns
t_TCP+4.0
ns
ns
150
ps
380
ps
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Typical values are given for V_CC = 3.3V and T_A = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD, ∆VOD,
VTH and VTL which are differential voltages.
Note 4: Due to TRI-STATE of the Serializer, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
Note 5: t_DJIT specifications are Guranteed By Design (GBD) using statistical analysis.
5
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