DS92LV1021A Datasheet, PDF (3/12 Pages) National Semiconductor (TI) – 16-40 MHz 10 Bit Bus LVDS Serializer

Resynchronization (Continued)
LOCK pin itself to control the sync request of the Serializer
(SYNC1 or SYNC2). At the time of publication, other than the
DS92LV1210, all other Deserializers from National Semicon-
ductor have random lock capability. This feature does not
require the system user to send SYNC patterns upon loss of
lock. However, lock times can only be guaranteed with trans-
mission of SYNC patterns. Dual SYNC pins are provided for
multiple control in a multi-drop application.
Powerdown
The Powerdown state is a low power sleep mode that the
Serializer and Deserializer may use to reduce power when
no data is being transferred. The device enters Powerdown
when the PWRDN pin is driven low on the Serializer. In
Ordering Information
Order Number NSID
DS92LV1021AMSA
Powerdown, the PLL stops and the outputs go into TRI-
STATE, disabling load current and reducing supply current
into the milliamp range. To exit Powerdown, PWRDN must
be driven high.
Both the Serializer and Deserializer must reinitialize and
resynchronize before data can be transferred. The Deserial-
izer will initialize and assert LOCK high until it is locked to the
Bus LVDS clock.
TRI-STATE
For the Serializer, TRI-STATE is entered when the DEN pin
is driven low. This will TRI-STATE both driver output pins
(DO+ and DO−). When DEN is driven high, the serializer will
return to the previous state as long as all other control pins
remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F).
Function
Serializer
Package
MSA28
3
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