DS92LV1021A Datasheet, PDF (11/12 Pages) National Semiconductor (TI) – 16-40 MHz 10 Bit Bus LVDS Serializer

Serializer Pin Description
Pin Name
DIN
TCLK_R/F
DO+
DO−
DEN
PWRDN
TCLK
SYNC
DVCC
DGND
AVCC
AGND
I/O
No.
Description
I
3–12
Data Input. TTL levels inputs. Data on these pins are loaded into a
10-bit input register.
I
13
Transmit Clock Rising/Falling strobe select. TTL level input. Selects
TCLK active edge for strobing of DIN data. High selects rising
edge. Low selects falling edge.
O
22
+ Serial Data Output. Non-inverting Bus LVDS differential output.
O
21
− Serial Data Output. Inverting Bus LVDS differential output.
I
19
Serial Data Output Enable. TTL level input. A low, puts the Bus
LVDS outputs in TRI-STATE.
I
24
Powerdown. TTL level input. PWRDN driven low shuts down the
PLL and TRI-STATEs the outputs putting the device into a low
power sleep mode. This pin has an internal weak pull down.
I
14
Transmit Clock. TTL level input. Input for 16 MHz–40 MHz
(nominal) system clock.
I
1, 2
Assertion of SYNC (high) for at least 1024 synchronization symbols
to be transmitted on the Bus LVDS serial output. Synchronization
symbols continue to be sent if SYNC continues asserted. TTL level
input. The two SYNC pins are ORed.
I
27, 28
Digital Circuit power supply. DVCC voltage level should be identical
to the AVCC voltage level.
I
15, 16
Digital Circuit ground. Ground potential should be the same as
AGND.
I
17, 26
Analog power supply (PLL and Analog Circuits). AVCC voltage
level should be identical to the DVCC voltage level.
I
18, 25, 20, 23 Analog ground (PLL and Analog Circuits). Ground potential should
be the same as DGND.
Truth Table
DIN (0–9)
X
X
X
DATA
DATA
TCLK_R/F
X
X
X
1
0
TCLK
X
X
SYSTEM CLK
L
K
SYNC1/SYNC2
X
X
1∼
0
0
DEN
X
0
1
1
1
PWRDN
0
1
1
1
1
DO+
Z
Z
SYNC PTRN
DATA (0–9)
DATA (0–9)
DO−
Z
Z
SYNC PTRN*
DATA (0–9)*
DATA (0–9)*
RI
RI−
X
X
X
X
SYNC PTRN SYNC PTRN*
DATA (0–9) DATA (0–9)*
DATA (0–9) DATA (0–9)*
∼ Pulse 5-bits
* Inverted
†Must be 1 before SYNC PTRN starts
** Device must be locked first
RCLK_R/F
X
X
X
1
0
REFCLK
X
X
SYSTEM CLK
SYSTEM CLK
SYSTEM CLK
REN
X
0**
1
1
1
PWRDN
0
1
1
1
1
RCLK
Z
Z
CLK
L
K
LOCK
Z
Z
1†
0
0
11
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