DS92LV1021A Datasheet, PDF (1/12 Pages) National Semiconductor (TI) – 16-40 MHz 10 Bit Bus LVDS Serializer

January 2003
DS92LV1021A
16-40 MHz 10 Bit Bus LVDS Serializer
General Description
The DS92LV1021A transforms a 10-bit wide parallel
LVCMOS/LVTTL data bus into a single high speed Bus
LVDS serial data stream with embedded clock. The
DS92LV1021A can transmit data over backplanes or cable.
The single differential pair data path makes PCB design
easier. In addition, the reduced cable, PCB trace count, and
connector size tremendously reduce cost. Since one output
transmits both clock and data bits serially, it eliminates clock-
to-data and data-to-data skew. The powerdown pin saves
power by reducing supply current when the device is not
being used. Upon power up of the Serializer, you can choose
to activate synchronization mode or use one of National
Semiconductor’s Deserializers in the synchronization-to-
random-data feature. By using the synchronization mode,
the Deserializer will establish lock to a signal within specified
lock times. In addition, the embedded clock guarantees a
transition on the bus every 12-bit cycle. This eliminates
transmission errors due to charged cable conditions. Fur-
thermore, you may put the DS92LV1021A output pins into
TRI-STATE^® to achieve a high impedance state. The PLL
can lock to frequencies between 16 MHz and 40 MHz.
Features
n Guaranteed transition every data transfer cycle
n Single differential pair eliminates multi-channel skew
n Flow-through pinout for easy PCB layout
n 400 Mbps serial Bus LVDS bandwidth (at 40 MHz clock)
n 10-bit parallel interface for 1 byte data plus 2 control bits
n Programmable edge trigger on clock
n Bus LVDS serial output rated for 27Ω load
n Small 28-lead SSOP package-MSA
Block Diagrams
TRI-STATE^® is a registered trademark of National Semiconductor Corporation.
© 2003 National Semiconductor Corporation DS200269
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