DS90CR211 Datasheet, PDF (9/14 Pages) National Semiconductor (TI) – 21-Bit Channel Link

AC Timing Diagrams (Continued)
FIGURE 16. Transmitter LVDS Output Pulse Position Measurement
DS012637-25
DS012637-26
SW — Setup and Hold Time (Internal data sampling window)
TCCS — Transmitter Output Skew
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)
Cable Skew — Typically 10 ps–40 ps per foot
FIGURE 17. Receiver LVDS Input Skew Margin
DS90CR211 Pin Description — Channel Link Transmitter (Tx)
Pin Name I/O No.
Description
TxIN
I 21 TTL Level inputs
TxOUT+
O 3 Positive LVDS differential data output
TxOUT−
O 3 Negative LVDS differential data output
TxCLK IN
I
1 TTL level clock input. The rising edge acts as data strobe
TxCLK OUT+ O 1 Positive LVDS differential clock output
TxCLK OUT− O 1 Negative LVDS differential clock output
PWR DOWN
I
1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down
V_CC
GND
I
4 Power supply pins for TTL inputs
I
5 Ground pins for TTL inputs
9
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