DS90CR211 Datasheet, PDF (10/14 Pages) National Semiconductor (TI) – 21-Bit Channel Link

DS90CR211 Pin Description — Channel Link Transmitter (Tx) (Continued)
Pin Name
PLL V_CC
PLL GND
LVDS V_CC
LVDS GND
I/O No.
I
1 Power supply pin for PLL
I
2 Ground pins for PLL
I
1 Power supply pin for LVDS outputs
I
3 Ground pins for LVDS outputs
Description
DS90CR212 Pin Description — Channel Link Receiver (Rx)
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V_CC
GND
PLL V_CC
PLL GND
LVDS V_CC
LVDS GND
I/O No.
Description
I
3 Positive LVDS differential data inputs
I
3 Negative LVDS differential data inputs
O 21 TTL level outputs
I
1 Positive LVDS differential clock input
I
1 Negative LVDS differential clock input
O 1 TTL level clock output. The rising edge acts as data strobe
I
1 TTL level input. Assertion (low input) maintains the receiver outputs in the previous state
I
4 Power supply pins for TTL outputs
I
5 Ground pins for TTL outputs
I
1 Power supply for PLL
I
2 Ground pin for PLL
I
1 Power supply pin for LVDS inputs
I
3 Ground pins for LVDS inputs
Applications Information
The Channel Link devices are intended to be used in a wide
variety of data transmission applications. Depending upon
the application the interconnecting media may vary. For ex-
ample, for lower data rate (clock rate) and shorter cable
lengths (< 2m), the media electrical performance is less criti-
cal. For higher speed/long distance applications the media’s
performance becomes more critical. Certain cable construc-
tions provide tighter skew (matched electrical length be-
tween the conductors and pairs). Twin-coax for example, has
been demonstrated at distances as great as 10 meters and
with the maximum data transfer of 1.12 Gbit/s. Additional ap-
plications information can be found in the following National
Interface Application Notes:
AN = ####
Topic
AN-1035
PCB Design Guidelines for LVDS and
Link Devices
AN-806
Transmission Line Theory
AN-905
Transmission Line Calculations and
Differential Impedance
AN-916
Cable Information
CABLES: A cable interface between the transmitter and re-
ceiver needs to support the differential LVDS pairs. The
21-bit CHANNEL LINK chipset (DS90CR211/212) requires
four pairs of signal wires and the 28-bit CHANNEL LINK
chipset (DS90CR281/282) requires five pairs of signal wires.
The ideal cable/connector interface would have a constant
100Ω differential impedance throughout the path. It is also
recommended that cable skew remain below 350 ps (@ 40
MHz clock rate) to maintain a sufficient data sampling win-
dow at the receiver.
In addition to the four or five cable pairs that carry data and
clock, it is recommended to provide at least one additional
conductor (or pair) which connects ground between the
transmitter and receiver. This low impedance ground pro-
vides a common mode return path for the two devices. Some
of the more commonly used cable types for point-to-point ap-
plications include flat ribbon, flex, twisted pair and
Twin-Coax. All are available in a variety of configurations and
options. Flat ribbon cable, flex and twisted pair generally per-
form well in short point-to-point applications while Twin-Coax
is good for short and long applications. When using ribbon
cable, it is recommended to place a ground line between
each differential pair to act as a barrier to noise coupling be-
tween adjacent pairs. For Twin-Coax cable applications, it is
recommended to utilize a shield on each cable pair. All ex-
tended point-to-point applications should also employ an
overall shield surrounding all cable pairs regardless of the
cable type. This overall shield results in improved transmis-
sion parameters such as faster attainable speeds, longer
distances between transmitter and receiver and reduced
problems associated with EMS or EMI.
The high-speed transport of LVDS signals has been demon-
strated on several types of cables with excellent results.
However, the best overall performance has been seen when
using Twin-Coax cable. Twin-Coax has very low cable skew
and EMI due to its construction and double shielding. All of
the design considerations discussed here and listed in the
supplemental application notes provide the subsystem com-
munications designer with many useful guidelines. It is rec-
ommended that the designer assess the tradeoffs of each
application thoroughly to arrive at a reliable and economical
cable solution.
BOARD LAYOUT: To obtain the maximum benefit from the
noise and EMI reductions of LVDS, attention should be paid
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