DS90CR211 Datasheet, PDF (12/14 Pages) National Semiconductor (TI) – 21-Bit Channel Link

Applications Information (Continued)
FIGURE 20. Single-Ended and Differential Waveforms
COMMON MODE vs. DIFFERENTIAL MODE NOISE MAR-
GIN: The typical signal swing for LVDS is 300 mV centered
at +1.2V. The CHANNEL LINK receiver supports a 100 mV
threshold therefore providing approximately 200 mV of differ-
ential noise margin. Common mode protection is of more im-
portance to the system’s operation due to the differential
data transmission. LVDS supports an input voltage range of
Ground to +2.4V. This allows for a ±1.0V shifting of the cen-
ter point due to ground potential differences and common
mode noise.
POWER SEQUENCING AND POWERDOWN MODE: Out-
puts of the CHANNEL LINK transmitter remain in
TRI-STATE^® until the power supply reaches 3V. Clock and
data outputs will begin to toggle 10 ms after V_CChas reached
4.5V and the Powerdown pin is above 2V. Either device may
be placed into a powerdown mode at any time by asserting
the Powerdown pin (active low). Total power dissipation for
each device will decrease to 5 µW (typical).
The CHANNEL LINK chipset is designed to protect itself
from accidental loss of power to either the transmitter or re-
ceiver. If power to the transmit board is lost, the receiver
clocks (input and output) stop. The data outputs (RxOUT) re-
tain the states they were in when the clocks stopped. When
the receiver board loses power, the receiver inputs are
shorted to V _CC through an internal diode. Current is limited
(5 mA per input) by the fixed current mode drivers, thus
avoiding the potential for latchup when powering the device.
DS012637-22
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