DS50EV401 Datasheet, PDF (9/14 Pages) National Semiconductor (TI) – 2.5 Gbps / 5.0 Gbps / 8.0 Gbps Quad PCI Express Cable and Backplane Equalizer

BEACON WAKEUP
The DS50EV401 signal path is designed to be broadband,
allowing a low frequency signal, such as the Beacon Wakeup
used by the PCI Express protocol, to pass through the device.
The AC coupling capacitors used to connect the DS50EV401
to the rest of the system limit the fidelity of the Beacon signal.
Therefore, a minimum capacitance of 75nF, as shown in fig-
ure 7, is required for proper operation.
FIGURE 7. Example of Passing Beacon Signal
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GENERAL RECOMMENDATIONS
The DS50EV401 is a high performance device capable of
delivering excellent performance. In order to extract full per-
formance from the device in a particular application, good
high-speed design practices must be followed. National
Semiconductor’s LVDS Owner's Manual, 4th edition provides
detailed information about managing signal integrity and pow-
er delivery to get the most from your design.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL
PAIRS
The CML inputs and outputs must have a controlled differen-
tial impedance of 100Ω. It is preferable to route CML lines
exclusively on one layer of the board, particularly for the input
traces. The use of vias should be avoided if possible. If vias
must be used, they should be used sparingly and must be
placed symmetrically for each side of a given differential pair.
Route the CML signals away from other signals and noise
sources on the printed circuit board. See AN-1187 for addi-
tional information on LLP packages..
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the
DS50EV401 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be
connected to power planes routed on adjacent layers of the
printed circuit board. The layer thickness of the dielectric
should be minimized so that the VDD and GND planes create
a low inductance supply with distributed capacitance. Sec-
ond, careful attention to supply bypassing through the proper
use of bypass capacitors is required. A 0.01μF bypass ca-
pacitor should be connected to each VDD pin such that the
capacitor is placed as close as possible to the DS50EV401.
Smaller body size capacitors can help facilitate proper com-
ponent placement. Additionally, three capacitors with capac-
itance in the range of 2.2 μF to 10 μF should be incorporated
in the power supply bypassing design as well. These capac-
itors can be either tantalum or an ultra-low ESR ceramic and
should be placed as close as possible to the DS50EV401.
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