DS50EV401 Datasheet, PDF (2/14 Pages) National Semiconductor (TI) – 2.5 Gbps / 5.0 Gbps / 8.0 Gbps Quad PCI Express Cable and Backplane Equalizer

Pin Descriptions
Pin Name Pin Number I/O, Type
HIGH SPEED DIFFERENTIAL I/O
IN_0+
1
I, CML
IN_0-
2
IN_1+
IN_1-
4
I, CML
5
IN_2+
IN_2-
8
I, CML
9
IN_3+
IN_3-
11
I, CML
12
OUT_0+
OUT_0-
36
O, CML
35
OUT_1+
OUT_1-
33
O, CML
32
OUT_2+
OUT_2-
29
O, CML
28
OUT_3+
OUT_3-
26
O, CML
25
EQUALIZATION CONTROL
MODE
14
I, CMOS
DEVICE CONTROL
EN0
44
I, CMOS
EN1
42
I, CMOS
EN2
40
I, CMOS
EN3
38
I, CMOS
SD0
SD1
SD2
SD3
POWER
V_DD
GND
Exposed
Pad
OTHER
Reserv
45
O, CMOS
43
O, CMOS
41
O, CMOS
39
O, CMOS
3, 6, 7,
10, 13,
15, 46
22, 24,
27, 30,
31, 34
PAD
Power
Power
Power
16, 17, 18,
19, 20, 21,
23, 37, 47,
48
Description
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 50Ω
terminating resistor connects IN_0+ to VDD and IN_0- to VDD.
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 50Ω
terminating resistor connects IN_1+ to VDD and IN_1- to VDD.
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 50Ω
terminating resistor connects IN_2+ to VDD and IN_2- to VDD.
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 50Ω
terminating resistor connects IN_3+ to VDD and IN_3- to VDD.
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_0+ to V_DD and OUT_0- to V_DD.
An on-chip 50Ω terminating resistor connects OUT_1+ to V_DD and OUT_1- to V_DD.
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_2+ to V_DD and OUT_2- to V_DD.
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_3+ to V_DD and OUT_3- to V_DD.
MODE selects the equalizer frequency for EQ channels. MODE is internally pulled low.
Enable Ch0 output driver input. When held High, normal operation is selected. When held
Low, Ch0 output drive is off and standby mode is selected. EN0 is internally pulled High.
Enable Ch1 output driver input. When held High, normal operation is selected. When held
Low, Ch1 output drive is off and standby mode is selected. EN1 is internally pulled High.
Enable Ch2 output driver input. When held High, normal operation is selected. When held
Low, Ch2 output drive is off and standby mode is selected. EN2 is internally pulled High.
Enable Ch3 output driver input. When held High, normal operation is selected. When held
Low, CH3 output drive is off and standby mode is selected. EN3 is internally pulled High.
Equalizer Ch0 Signal Detect Output. Produces a High when signal is detected.
Equalizer Ch1 Signal Detect Output. Produces a High when signal is detected.
Equalizer Ch2 Signal Detect Output. Produces a High when signal is detected.
Equalizer Ch3 Signal Detect Output. Produces a High when signal is detected.
V_DD = 2.5V ± 5% or 3.3V ± 10%. V_DD pins should be tied to V_DD plane through low inductance
path. A 0.01μF bypass capacitor should be connected between each V_DD pin to GND planes.
Ground reference. GND should be tied to a solid ground plane through a low impedance
path.
Ground reference. The exposed pad at the center of the package must be connected to
ground plane of the board.
Reserved. Do not connect.
Note: I = Input O = Output
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