DS50EV401 Datasheet, PDF (5/14 Pages) National Semiconductor (TI) – 2.5 Gbps / 5.0 Gbps / 8.0 Gbps Quad PCI Express Cable and Backplane Equalizer

Symbol
Parameter
Conditions
Min
Typ
Max
CML OUTPUTS (OUT_n+, OUT_n-)
V_O
Output Voltage Swing
Differential measurement with
OUT_n+ and OUT_n- terminated
800
by 50Ω to GND AC-Coupled
(Figure 2)
1200
V_OCM
Output Common-Mode Voltage
Single-ended measurement DC-
Coupled with 50Ω termination
(Note 6)
V_DD – 0.25
t_R, t_F
Transition Time
20% to 80% of differential output
voltage, measured within 1” from
40
output pins
(Figure 2) (Note 6)
R_O
Output Resistance
Single-ended to V_DD
40
50
60
R_LO
Differential Output Return Loss 100 MHz – 4.0 GHz, with fixture’s
effect de-embedded. IN_n+ =
10
static high
t_PLHD
Differential Low to High
Propagation Delay
Propagation delay measurement
at 50% V_O between input to output,
240
t_PHLD
Differential High to Low
Propagation Delay
100 Mbps
(Figure 3) (Note 8)
240
t_ID
Idle to Valid Differential Data
VIN = 800 mVp-p, 5 Gbps, EIEOS,
40” of 6 mil microstrip FR4
8
(Figure 4) (Note 6)
t_DI
Valid Differential data to idle
VIN = 800 mVp-p, 5 Gbps, EIOS,
40” of 6 mil microstrip FR4
8
(Figure 4) (Note 6)
t_CCSK
Inter Pair Channel to Channel
Skew
Difference in 50% crossing
between channels
7
EQUALIZATION
DJ1
Residual Deterministic Jitter at 8 30” of 6 mil microstrip FR4,
Gbps
MODE=0, PRBS-7 (2⁷-1) pattern
0.18
(Note 6, 7)
DJ2
Residual Deterministic Jitter at 5 40” of 6 mil microstrip FR4,
Gbps
MODE=1, PRBS-7 (2⁷-1) pattern
(Note 6, 7)
0.18
0.21
DJ3
Residual Deterministic Jitter at 2.5 40” of 6 mil microstrip FR4,
Gbps
MODE=1, PRBS-7 (2⁷-1) pattern
(Note 6, 7)
0.16
0.18
RJ
Random Jitter
(Note 8, 9)
0.5
Units
mV_P-P
V
ps
Ω
dB
ps
ps
ns
ns
ps
UI_P-P
UI_P-P
UI_P-P
psrms
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. Absolute Maximum Numbers are guaranteed for a junction temperature range of -40°C to +125°C. Models
are validated to Maximum Operating Voltages only.
Note 2: Typical values represent most likely parametric norms at V_DD = 3.3V or 2.5V, T_A = 25°C., and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 3: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 4: Allowed supply noise (mV_P-P sine wave) under typical conditions.
Note 5: V_IN-S is a measurement of the input differential envelope (Figure 10). The device does not require an open eye.
Note 6: Specification is guaranteed by characterization at optimal MODE setting and is not tested in production.
Note 7: Deterministic jitter is measured at the differential outputs (point C of Figure 1), minus the deterministic jitter before the test channel (point A of Figure 1).
Random jitter is removed through the use of averaging or similar means.
Note 8: Measured with clock-like {11111 00000} pattern.
Note 9: Random jitter contributed by the equalizer is defined as sqrt (J_OUT2 – J_IN2). J_OUT is the random jitter at equalizer outputs in ps-rms, see point C of Figure
1; J_IN is the random jitter at the input of the equalizer in ps-rms, see point B of Figure 1.
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