DS50EV401 Datasheet, PDF (8/14 Pages) National Semiconductor (TI) – 2.5 Gbps / 5.0 Gbps / 8.0 Gbps Quad PCI Express Cable and Backplane Equalizer

DS50EV401 Applications
Information
The DS50EV401 is a programmable quad equalizer opti-
mized for PCI Express applications. It is designed to operate
over copper backplanes and cables at transmission rates of
2.5 Gbps up to 8 Gbps. The device consists of an input re-
ceive equalizer followed by a limiting amplifier. The equalizer
is designed to open an input eye that is completely closed due
to inter-symbol interference (ISI) induced by the channel in-
terconnect. The equalization is set to keep residual determin-
istic jitter below 0.2 unit intervals (UI) regardless of data rate.
This equalization scheme allows 1 equalization setting to sat-
isfy both Gen1 and Gen2 links, eliminating the need for inter-
action between the equalizer and PCI Express endpoint
during link negotiation. The DS50EV401 is intended as a uni-
directional receiver that should be placed in close physical
proximity to the end point. Therefore the transmitter does not
include de-emphasis as TX equalization would not be needed
over the short distance between the equalizer and the end
point.
In order to enable PCI compliant link extension the
DS50EV401 will put the transmitter into electrical idle mode
when no active data is sensed on its inputs. Idle is controlled
on a per lane basis, and is solely dependent on activity of a
particular channel’s input activity. 50 ohm termination is main-
tained on both the RX and TX terminals in electrical idle mode.
The DS50EV401 internal signal path is designed to be broad
band, allowing the Beacon Wakeup signal to pass through to
the endpoint device.
FIGURE 5. Simplified Block Diagram
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DATA CHANNELS
The DS50EV401 consists of four data channels. Each chan-
nel provides input termination, receiver equalization, signal
limiting, offset cancellation, and a CML output driver, as
shown in Figure 5. The data channels support two levels of
equalization, controlled by the pin MODE. The equalization
levels are set simultaneously on all 4 channels, as described
in Table 1.
When an idle condition is sensed on a channel’s input, the
transmit driver is automatically placed into electrical idle
mode, as shown in Figure 6. The common mode voltage is
set, and the differential output is forced to zero. To save pow-
er, the output driver current is powered off when the device is
in electrical idle mode. All other circuits maintain their bias
currents allowing a fast recovery from idle to the active state.
Electric idle is performed on a per channel basis, and several
channels can be in idle while others are actively passing data.
TABLE 1. MODE Control Table
6 mil microstrip FR4
trace length (in)
0–30
0–40
24 AWG Twin-AX cable
length (m)
0–7
0–10
Frequency
8 Gbps
5 Gbps
2.5 Gbps
Channel Loss
16 dB
14 dB
20 dB
MODE
0
1
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FIGURE 6. Automatic Power Management
8
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