COP87L84RG Datasheet, PDF (9/40 Pages) National Semiconductor (TI) – 8-Bit One-Time Programmable (OTP) Microcontroller with 32 Kbytes of Program Memory

Reset (Continued)
Ports being initialized to the TRI-STATE mode Pin G1 of the
G Port is an exception (as noted below) since pin G1 is
dedicated as the WATCHDOG and or Clock Monitor error
output pin Port D is set high The PC PSW ICNTRL
CNTRL T2CNTRL and T3CNTRL control registers are
cleared The UART registers PSR ENU (except that TBMT
bit is set) ENUR and ENUI are cleared The Comparator
Select Register is cleared The S register is initialized to
zero The Multi-Input Wake Up registers WKEN WKEDG
and WKPND are cleared The stack pointer SP is initialized
to 6F Hex
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed with the
WATCHDOG service window bits set and the Clock Monitor
bit set The WATCHDOG and Clock Monitor circuits are in-
hibited during reset The WATCHDOG service window bits
being initialized high default to the maximum WATCHDOG
service window of 64k t_c clock cycles The Clock Monitor bit
being initialized high will cause a Clock Monitor error follow-
ing reset if the clock has not reached the minimum specified
frequency at the termination of reset A Clock Monitor error
will cause an active low error output on pin G1 This error
output will continue until 16 t_c – 32 t_c clock cycles following
the clock frequency reaching the minimum specified value
at which time the G1 output will enter the TRI-STATE mode
The external RC network shown in Figure 6 should be used
to ensure that the RESET pin is held low until the power
supply to the chip stabilizes
Note Continual state of reset will cause the device to draw excessive cur-
rent
RC l 5 c Power Supply Rise Time
TL DD 12872 – 6
FIGURE 6 Recommended Reset Circuit
Oscillator Circuits
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz The CKO output
clock is on pin G7 (crystal configuration) The CKI input fre-
quency is divided down by 10 to produce the instruction
cycle clock (1 t_c)
Figure 7 shows the Crystal and R C diagrams
CRYSTAL OSCILLATOR
CKI and CKO can be connected to make a closed loop
crystal (or resonator) controlled oscillator
Table I shows the component values required for various
standard crystal values
TABLE I Crystal Oscillator Configuration T_A e 25 C
R1 R2 C1
C2 CKI Freq
Conditions
(kX) (MX) (pF) (pF)
(MHz)
0
1 30 30 – 36
10
V_CC e 5V
0
1 30 30 – 36
4
V_CC e 5V
0
1 200 100 – 150 0 455 V_CC e 5V
R C OSCILLATOR
By selecting CKI as a single pin oscillator input a single pin
R C oscillator circuit can be connected to it CKO is avail-
able as a general purpose input and or HALT restart pin
Table II shows the variation in the oscillator frequencies as
functions of the component (R and C) values
TABLE II R C Oscillator Configuration T_A e 25 C
R
C CKI Freq Instr Cycle _Conditions
(kX) (pF) (MHz)
(ms)
3 3 82 2 2 – 2 7
5 6 100 1 1 – 1 3
6 8 100 0 9 – 1 1
Note 3k s R s 200k
50 pF s C s 200 pF
3 7–4 6
7 4–9 0
8 8 – 10 8
V_CC e 5V
V_CC e 5V
V_CC e 5V
Control Registers
CNTRL Register (Address X 00EE)
The Timer1 (T1) and MICROWIRE PLUS control register
contains the following bits
SL1 SL0 Select the MICROWIRE PLUS clock divide
by (00 e 2 01 e 4 1x e 8)
IEDG
External interrupt edge polarity select
(0 e Rising edge 1 e Falling edge)
MSEL
Selects G5 and G4 as MICROWIRE PLUS
signals
SK and SO respectively
T1C0
Timer T1 Start Stop control in timer
modes 1 and 2
Timer T1 Underflow Interrupt Pending Flag in
timer mode 3
T1C1
Timer T1 mode control bit
T1C2
Timer T1 mode control bit
T1C3
Timer T1 mode control bit
T1C3 T1C2 T1C1 T1C0 MSEL IEDG SL1 SL0
Bit 7
Bit 0
TL DD12872 – 7
FIGURE 7 Crystal and R C Oscillator Diagrams
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