COP87L84RG Datasheet, PDF (14/40 Pages) National Semiconductor (TI) – 8-Bit One-Time Programmable (OTP) Microcontroller with 32 Kbytes of Program Memory

Power Save Modes (Continued)
The WATCHDOG detector circuit is inhibited during the
HALT mode However the clock monitor circuit if enabled
remains active during HALT mode in order to ensure a clock
monitor error if the device inadvertently enters the HALT
mode as a result of a runaway program or power glitch
IDLE MODE
The device is placed in the IDLE mode by writing a ‘‘1’’ to
the IDLE flag (G6 data bit) In this mode all activities except
the associated on-board oscillator circuitry the
WATCHDOG logic the clock monitor and the IDLE Timer
T0 are stopped The power supply requirements of the mi-
cro-controller in this mode of operation are typically around
30% of normal power requirement of the microcontroller
As with the HALT mode the device can be returned to nor-
mal operation with a reset or with a Multi-Input Wake Up
from the L Port Alternately the microcontroller resumes
normal operation from the IDLE mode when the thirteenth
bit (representing 4 096 ms at internal clock frequency of
1 MHz t_c e 1 ms) of the IDLE Timer toggles
This toggle condition of the thirteenth bit of the IDLE Timer
T0 is latched into the T0PND pending flag
The user has the option of being interrupted with a transition
on the thirteenth bit of the IDLE Timer T0 The interrupt can
be enabled or disabled via the T0EN control bit Setting the
T0EN flag enables the interrupt and vice versa
The user can enter the IDLE mode with the Timer T0 inter-
rupt enabled In this case when the T0PND bit gets set the
device will first execute the Timer T0 interrupt service rou-
tine and then return to the instruction following the ‘‘Enter
Idle Mode’’ instruction
Alternatively the user can enter the IDLE mode with the
IDLE Timer T0 interrupt disabled In this case the device
will resume normal operation with the instruction immediate-
ly following the ‘‘Enter IDLE Mode’’ instruction
Note It is necessary to program two NOP instructions following both the set
HALT mode and set IDLE mode instructions These NOP instructions
are necessary to allow clock resynchronization following the HALT or
IDLE modes
Due to the on-board 8k EPROM with port recreation logic
the HALT IDLE current is much higher compared to the
equivalent masked port
Multi-Input Wake Up
The Multi-Input Wake Up feature is ued to return (Wake Up)
the device from either the HALT or IDLE modes Alternately
Multi-Input Wake Up Interrupt feature may also be used to
generate up to 8 edge selectable external interrupts
Figure 11 shows the Multi-Input Wake Up logic The Multi-
Input Wake Up feature utilizes the L Port The user selects
which particular L port bit (or combination of L Port bits) will
cause the device to exit the HALT or IDLE modes The se-
lection is done through the Reg WKEN The Reg WKEN
FIGURE 11 Multi-Input Wake Up Logic
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