COP87L84RG Datasheet, PDF (22/40 Pages) National Semiconductor (TI) – 8-Bit One-Time Programmable (OTP) Microcontroller with 32 Kbytes of Program Memory

Comparators (Continued)
CMPSL REGISTER (ADDRESS X’00B7)
The CMPSL register contains the following bits
CMP1EN Enable comparator
CMP1RD Comparator result (this is a read only bit which
will read as 0 if the comparator is not enabled)
CMP10E Selects pin I3 as comparator output provided
that CMPIEN is set to enable the comparator
Unused Unused Unused Unused CMP10E CMP1RD CMP1EN Unused
Bit 7
Bit 0
Note that the two unused bits of CMPSL may be used as
software flags
Comparator output has the same spec as Ports L and G
except that the rise and fall times are symmetrical
Interrupts
The devices support a vectored interrupt scheme It sup-
ports a total of fourteen interrupt sources The following ta-
ble lists all the possible device interrupt sources their arbi-
tration ranking and the memory locations reserved for the
interrupt vector for each source
Two bytes of program memory space are reserved for each
interrupt source All interrupt sources except the software
interrupt are maskable Each of the maskable interrupts
have an Enable bit and a Pending bit A maskable interrupt
is active if its associated enable and pending bits are set If
GIE e 1 and an interrupt is active then the processor will
be interrupted as soon as it is ready to start executing an
instruction except if the above conditions happen during the
Software Trap service routine This exception is described
in the Software Trap sub-section
The interruption process is accomplished with the INTR in-
struction (opcode 00) which is jammed inside the Instruc-
tion Register and replaces the opcode about to be execut-
ed The following steps are performed for every interrupt
1 The GIE (Global Interrupt Enable) bit is reset
2 The address of the instruction about to be executed is
pushed into the stack
3 The PC (Program Counter) branches to address 00FF
This procedure takes 7 t_c cycles to execute
Arbitration
Ranking
(1) Highest
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16) Lowest
Source
Software
Reserved
External
Timer T0
Timer T1
Timer T1
MICROWIRE PLUS
Reserved
UART
UART
Timer T2
Timer T2
Timer T3
Timer T3
Port L Wake Up
Default
y is VIS page y i 0
Description
INTR Instruction
for Future Use
Pin G0 Edge
Underflow
T1A Underflow
T1B
BUSY Goes Low
for Future Use
Receive
Transmit
T2A Underflow
T2B
T3A Underflow
T3B
Port L Edge
VIS Instr Execution
without Any Interrupts
Vector
Address
Hi-Low Byte
0yFE – 0yFF
0yFC – 0yFD
0yFA – 0yFB
0yF8 – 0yF9
0yF6 – 0yF7
0yF4 – 0yF5
0yF2 – 0yF3
0yF0 – 0yF1
0yEE – 0yEF
0yEC – 0yED
0yEA – 0yEB
0yE8 – 0yE9
0yE6 – 0yE7
0yE4 – 0yE5
0yE2 – 0yE3
0yE0 – 0yE1
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