COP87L84RG Datasheet, PDF (28/40 Pages) National Semiconductor (TI) – 8-Bit One-Time Programmable (OTP) Microcontroller with 32 Kbytes of Program Memory

Memory Map
All RAM ports and registers (except A and PC) are mapped into data memory address space
Address
S ADD REG
0000 to 006F
0070 to 007F
xx80 to xxAF
xxB0
xxB1
xxB2
xxB3
xxB4
xxB5
xxB6
xxB7
xxB8
xxB9
xxBA
xxBB
xxBC
xxBD
xxBE
xxBF
xxC0
xxC1
xxC2
xxC3
xxC4
xxC5
xxC6
xxC7
xxC8
xxC9
xxCA
xxCB
xxCC
xxCD to xxCF
Contents
On-Chip RAM bytes (112 bytes)
Unused RAM Address Space (Reads
As All Ones)
Unused RAM Address Space (Reads
Undefined Data)
Timer T3 Lower Byte
Timer T3 Upper Byte
Timer T3 Autoload Register T3RA
Lower Byte
Timer T3 Autoload Register T3RA
Upper Byte
Timer T3 Autoload Register T3RB
Lower Byte
Timer T3 Autoload Register T3RB
Upper Byte
Timer T3 Control Register
Comparator Select Register (CMPSL)
UART Transmit Buffer (TBUF)
UART Receive Buffer (RBUF)
UART Control and Status Register
(ENU)
UART Receive Control and Status
Register (ENUR)
UART Interrupt and Clock Source
Register (ENUI)
UART Baud Register (BAUD)
UART Prescale Select Register (PSR)
Reserved for UART
Timer T2 Lower Byte
Timer T2 Upper Byte
Timer T2 Autoload Register T2RA
Lower Byte
Timer T2 Autoload Register T2RA
Upper Byte
Timer T2 Autoload Register T2RB
Lower Byte
Timer T2 Autoload Register T2RB
Upper Byte
Timer T2 Control Register
WATCHDOG Service Register
(Reg WDSVR)
MIWU Edge Select Register
(Reg WKEDG)
MIWU Enable Register (Reg WKEN)
MIWU Pending Register
(Reg WKPND)
Reserved
Reserved
Reserved
Address
S ADD REG
Contents
xxD0
xxD1
xxD2
xxD3
xxD4
xxD5
xxD6
xxD7
xxD8
xxD9
xxDA
xxDB
xxDC
xxDD to DF
Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Reserved
Reserved
Reserved
Reserved
Port D
Reserved for Port D
xxE0 to xxE5
xxE6
xxE7
xxE8
xxE9
xxEA
xxEB
xxEC
xxED
xxEE
xxEF
Reserved for EE Control Registers
Timer T1 Autoload Register T1RB
Lower Byte
Timer T1 Autoload Register T1RB
Upper Byte
ICNTRL Register
MICROWIRE PLUS Shift Register
Timer T1 Lower Byte
Timer T1 Upper Byte
Timer T1 Autoload Register T1RA
Lower Byte
Timer T1 Autoload Register T1RA
Upper Byte
CNTRL Control Register
PSW Register
xxF0 to FB
xxFC
xxFD
xxFE
xxFF
On-Chip RAM Mapped as Registers
X Register
SP Register
B Register
S Register
0100 – 017F On-Chip 128 RAM Bytes
Note Reading memory locations 0070H–007FH (Segment 0) will return all
ones Reading unused memory locations 0080H–00AFH (Segment 0) will
return undefined data Reading memory locations from other Segments (i e
Segment 2 Segment 3 etc ) will return all ones
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